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| 型号： | TLV990APFB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | PLASTIC, TQFP-48 |
| 文件页数： | 8/24页 |
| 文件大小： | 328K |
| 代理商： | TLV990APFB |
TLV990A
3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR
SLAS297 – SEPTEMBER 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
CCD mode operation
The output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. The
CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting
two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor and
obtains the voltage difference between the CCD reference level and the video level of each pixel. Two
sample/hold control pulses (SR and SV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLV990A. The ac-coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990A is set
to 1.2 V. Normally, CLCCD is applied at sensor’s line rate. A capacitor, with a value ten times larger than that
of the input ac-coupling capacitor, should be connected between the CLREF pin and the AGND.
When operating the TLV990A at its maximum speed, the CCD internal source resistance should be smaller than
50
. Otherwise CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB
by programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit resolution
on a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation,
Gain = PGA code
× 0.045 dB
Where PGA code has a range of 0 to 767.
Due to different exposure times, there might be a sudden optical black level shift at the start of each frame. Thus,
a quick optical black-level correction is desirable. The user can set an internal control bit (the SOF bit in control
register2) to automatically disable the hot/cold pixel limits and to set the digital filtering weighting factor to 1
(equivalent to one-line averaging). In this way the optical black correction could be performed very quickly for
the first line of each frame.
The number pf black pixels in each line is programmable. The number of black pixels per line that can be
averaged is 2N, where N can be any integer between 0 and 6.
The autocalibration feature can be bypassed if the user prefers to directly program the offset DAC registers.
Switching the autocalibration mode to the direct programming mode requires two register writes. First, the
control bits for the offset DACs in the control register must be changed, then the desired register-offset value
is loaded to the offset DAC registers for proper error correction. If the total offset, including optical black level,
is less than
±255 ADC LSBs, only the FDAC needs to be programmed. When switching from direct programming
mode to autocalibration mode, the previous DAC register values are used as starting offsets rather than default
DAC register values.
video mode operation
The TLV990A also provides an analog video-processing channel that consists of an input clamp, a PGA, and
an ADC. Setting the INM bit to 1 in control register2 enables the video channel. The video signal should be
connected to the VIDEOIN pin via a 0.1-
F capacitor, as shown in Figure 5.
The video input has its own clamp circuit operated in two modes: autoclamp, and manual clamp.
In manual clamp mode, the input is clamped when CLVDO pin is pulled low. During this mode, the dc level of
the video sync pulse is forced to the clamp reference voltage (1.2 V).
If the dc level of the video sync pulse is less than the clamp voltage (1.2 V), the autoclamp mode can be selected
(control register2). No external clamp-control signal is required. The CLVDO pin can be left open.
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