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| 型号： | TMP86CP23AUG |
| 厂商： | Toshiba Corporation |
| 英文描述： | Zener Diode; Application: General; Pd (mW): 500; Vz (V): 1.8 to 2.0; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
| 中文描述： | 8位微控制器 |
| 文件页数： | 94/204页 |
| 文件大小： | 2324K |
| 代理商： | TMP86CP23AUG |
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Page 84
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86CP23AUG
8.3.4
Frequency Measurement mode
In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by
TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to “00”.
An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate
pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of
TREG1A while the count is stopped (window gate pulse is low), then clear the counter using
TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.
The window pulse status can be monitored by TC1SR<HECF>.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,
TC1SR<HEOVF> is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be
cleared by TC1CR1<TC1C>.
Using TC6 output (
PWM6
/
PDO6
/
PPG6
) for the window gate pulse, external output of
PWM6
/
PDO6
/
PPG6
to
P33 can be controlled using TC1CR2<TC6OUT>. Zero-clearing TC1CR2<TC6OUT> outputs
PWM6
/
PDO6
/
PPG6
to P33; setting 1 in TC1CR2<TC6OUT> does not output
PWM6
/
PDO6
/
PPG6
to P33.
(TC1CR2<TC6OUT> is used to control output to P33 only. Thus, use the timer counter 6 control register to
operate/stop
PWM6
/
PDO6
/
PPG6
.)
When the internal window gate pulse is selected, the window gate pulse is set as follows.
The internal window gate pulse consists of “H” level period (Ta) that is counting time and “L” level period
(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.
Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be
delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer.
Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When
Tb is overwritten during the Tb period, the update is valid from the next Tb period.
Note 3: In case of TC1CR2<SEG> = "1", if window gate pulse becomes falling edge, the up counter stops plus "1"
regardless of ECIN input level. Therefore, if ECIN is always "H" or "L" level, count value becomes "1".
Note 4: In case of TC1CR2<SEG> = "0", because the up counter is counted on the falling edge of logical AND-ed
pulse (between ECIN pin input and window gate pulse), if window gate pulse becomes falling edge while
ECIN input is "H" level, the up counter stops plus "1". Therefore, if ECIN input is always "H" level, count
value becomes "1".
Table 8-2 Internal window gate pulse setting time
WGPSCK
NORMAL1/2,IDLE1/2 modes
SLOW1/2,
SLEEP1/2 modes
R/W
DV7CK=0
DV7CK=1
Ta
Setting "H" level period of the window
gate pulse
00
01
10
(16 - Ta)
×
2
12
/fc
(16 - Ta)
×
2
13
/fc
(16 - Ta)
×
2
14
/fc
(16 - Ta)
×
2
4
/fs
(16 - Ta)
×
2
5
/fs
(16 - Ta)
×
2
6
/fs
(16 - Ta)
×
2
4
/fs
(16 - Ta)
×
2
5
/fs
(16 - Ta)
×
2
6
/fs
Tb
Setting "L" level period of the window
gate pulse
00
01
10
(16 - Tb)
×
2
12
/fc
(16 - Tb)
×
2
13
/fc
(16 - Tb)
×
2
14
/fc
(16 - Tb)
×
2
4
/fs
(16 - Tb)
×
2
5
/fs
(16 - Tb)
×
2
6
/fs
(16 - Tb)
×
2
4
/fs
(16 - Tb)
×
2
5
/fs
(16 - Tb)
×
2
6
/fs
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