70
TOSHIBA CORPORATION
TMP96C031N/F
Comparator
A comparator compares the value in the up-counter
with the values to which the timer register is set. When
they match, the up-counter is cleared to zero and an
interrupt signal (INTT0, INTT1, INTT2, INTT3) is gener-
ated. If the timer flip-flop inversion is enabled, the timer
flip-flop is inverted at the same time.
Timer flip-flops (timer F/F)
The timer flip-flops are inverted according to the
interval timer match detect signal (comparator output).
The signal can output a value to the timer output pins
TO1 (also used as P70) and TO3 (also used as P71).
There are two timer flip-flops: TFF1 for timers 0 and
1; TFF3 for timers 2 and 3. TFF1 is output to the TO1 pin;
TFF3 to the TO3 pin.
TO3 (also used as P71) is multiplexed using the
DMUX pin; setting must be done using the port 7 control
registers (P7CRL and P7CRH).
The operation of 8-bit timers will be described below:
(1)
8-bit timer mode
Four interval timers 0, 1, 2, 3, can be used indepen-
dently as 8-bit interval timer. All interval timers operate
in the same manner, and thus only the operation of
timer 1 will be explained below.
Generating interrupts in a fixed cycle
To generate timer 1 interrupt at constant intervals using
timer 1 (INTT1), first stop timer 1 then set the operation
mode, input clock, and a cycle to T01MOD and
TREG1 register, respectively. Then, enable interrupt
INTT1 and start the counting of timer 1.
Example: To generate timer 1 interrupt every 40
microseconds at fc = 16MHz, set each
register in the following manner.
Note:
x; don’t care –; no change
MSB
7
–
0
LSB
0
–
–
6
–
0
5
–
x
4
–
x
3
–
0
2
–
1
1
0
–
TRUN
T01MOD
←
←
Stop timer 1, and clear it to “0”.
Set the 8-bit timer mode, and select
(0.5
μ
s @ fc = 16MHz) as the input clock.
Set the timer register at 40
Enable INTT1, and set it to “Level 5”.
Start timer 1 counting.
φ
T1
TREG1
INTET10
TRUN
←
←
←
0
1
x
1
1
x
1
0
1
0
1
–
1
–
–
0
–
–
0
–
1
0
–
–
μ
s
φ
T1 = 50H.
Use the following table for selecting the input clock.
Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock
Input Clock
Interrupt Cycle
(at fc = 20MHz)
Resolution
φ
φ
T4 (32/fc)
φ
T16 (128/fc)
φ
T256 (2048/fc)
T1 (8/fc)
0.4
1.6
μ
s ~ 409.6
μ
s
6.4
μ
s ~ 1.638ms
102.4
μ
s ~ 2.621ms
μ
s ~ 102.4
μ
s
0.4
μ
s
1.6
μ
s
6.4
μ
s
102.4
μ
s