TOSHIBA CORPORATION
87
TMP96C031N/F
Capture Input Control
This circuit controls the timing to latch the value of up-
counter UC4 into (CAP1, CAP2). The latch timing of
capture register is controlled by register T4MOD
<CAP12M 1, 0>/T5MOD <CAP34M1,0>.
When T4MOD <CAP12M 1, 0> = 00
Capture function is disabled. Disable is the default on
reset.
When T4MOD <CAP12M1, 0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin
(also used P80/INT4) input, while data is loaded to
CAP2 at the rise edge of TI5 pin (also used as P81/
INT5) and input. (Time difference measurement)
When T4MOD <CAP12M1, 0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin
input, while to CAP2 at the fall edge. Only in this set-
ting, interrupt INT4 occurs at fall edge. (Pulse width
measurement)
When T4MOD <CAP12M1, 0> = 11
Data is loaded to CAP1 at the rise edge of timer flip-
flop TFF1, while to CAP2 at the fall edge.
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAP1IN> the current value of up-counter
will be loaded to capture register CAP1. It is neces-
sary to keep the prescaler in RUN mode (TRUN
<PRRUN> to be “1”).
Comparator
These are 16-bit comparators which compare the up-
counter UC4 value with the set value of (TREG4,
TREG5) to detect the match. When a match is
detected, the comparators generate and interrupt
(INTT4, INTT5) respectively. The up-counter UC4 is
cleared only when UC4 matches TREG5. (The clear-
ing of up-counter UC4 can be disabled by setting
T4MOD <CLE> = 0.)
Timer flip-flop (TFF4)
This flip-flop is inverted by the match detect signal
from the comparators and the latch signals to the
capture registers. Disable/enable of inversion can be
set for each element by T4FFCR <CAP2T4, CAP1T4,
EQ5T4, EQ4T4>. TFF4 will be inverted when “00” is
written in T4FFCR <TFF4C1,0>. Also it is set to “1”
when “10” is written, and cleared to “0” when “10” is
written. The value of TFF4 can be output to the timer
output pin TO4 (also used as P70).
Timer flip-flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator and the latch signal to the cap-
ture register CAP2. TFF5 will be inverted when “00” is
written in T4FFCR <TFF5C1,0>/T6FFCR
<TFF6C1,0>. Also it is set to “1” when “10” is written,
and cleared to “0” when “10” is written. The value of
TFF5 can be output to the timer output pin TO5 (also
used as P82).
TO5 (also used as P30) is multiplexed using the HWR
pin; setting must be done using the port 3 control reg-
ister, P3CRL.
Note: TO5 (also used as P30) is multiplexed with HWR; setting
must be done using the P3SR.