参数资料
型号: TMR320R2812PGFA
厂商: Texas Instruments, Inc.
元件分类: 数字信号处理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812数字信号处理器
文件页数: 139/147页
文件大小: 2021K
代理商: TMR320R2812PGFA
Electrical Specifications
139
June 2004
SPRS257
Table 6
47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
P-10
P-10
MAX
MIN
8P-10
8P-10
MAX
M39
M40
t
su(DRV-CKXH)
t
h(CKXH-DRV)
t
su(FXL-CKXH)
t
c(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
M41
Setup time, FSX low before CLKX high
16P+10
ns
M42
Cycle time, CLKX
2P
16P
ns
Table 6
48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M34
M35
t
h(CKXL-FXL)
t
d(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit
from CLKX low
P
ns
ns
2P
M37
t
dis(CKXL-DXHZ)
P + 6
7P+6
ns
M38
t
d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB
MSB
M41
M42
Figure 6
41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
A
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