参数资料
型号: TMR320R2812PGFQ
厂商: Texas Instruments, Inc.
元件分类: 数字信号处理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812数字信号处理器
文件页数: 46/147页
文件大小: 2021K
代理商: TMR320R2812PGFQ
Functional Overview
46
June 2004
SPRS257
X2
X1/XCLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
XF_XPLLDIS
OSCCLK (PLL Disabled)
Latch
XPLLDIS
XRS
PLL
4-Bit PLL Select
SYSCLKOUT
1
0
CLKIN
CPU
4-Bit PLL Select
XCLKIN
PLL Block
Figure 3
8. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to R281x devices using the X1/XCLKIN and X2
pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and
the X2 pin is left unconnected. The logic-high level in this case should not exceed V
DD
. The PLLCR bits [3:0]
set the clocking ratio.
Table 3
12. PLLCR Register Bit Definitions
BIT(S)
15:4
NAME
reserved
TYPE
R = 0
XRS RESET
0:0
DESCRIPTION
3:0
DIV
R/W
0,0,0,0
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
The PLLCR register is reset to a known state by the XRS reset line.
If a reset is issued by the debugger, the PLL clocking ratio is not changed.
3.7.2
Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1
4 MHz. The PLLCR register should have been written to with a non-zero value for this feature
to work.
A
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