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参数资料
| 型号： | TMS29F800T-100CDCDQ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| 中文描述： | 1048576 8位/ 524288由16位闪存 |
| 文件页数： | 18/51页 |
| 文件大小： | 685K |
| 代理商： | TMS29F800T-100CDCDQ |
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
exceed time limit (DQ5)
Program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the
pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase
operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop
toggling when read. To continue operation, the device must be reset.
The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been
programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After
reset, the device is functional and can be erased and reprogrammed.
sector-load-timer (DQ3)
The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses
has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 100
μ
s.
This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates
that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the
sector-erase command section for a description.
The data-polling and toggle bit are valid during the 100-
μ
s time delay and can be used to determine if a valid
sector-erase command has been issued. To ensure additional sector-erase commands have been accepted,
the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic
low on both reads, the additional sector-erase command was accepted.
toggle bit 2 (DQ2)
The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2
toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter
that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to the
timer-exceed limit, and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5
failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended
sector causes a logic high on DQ2.
ready/busy bit (RY/BY)
The RY/BY bit indicates when the device can accept new commands after performing algorithmic operations.
If the RY/BY (open-drain output) bit is low, the device is busy with either a program or erase operation and does
not accept any other commands except for erase suspend. While it is in the erase-suspend mode, RY/BY
remains high. In program mode, the RY/BY bit is valid (logic low) after the fourth WE pulse. In erase mode, it
is valid after the sixth WE pulse. After a delay period, t
busy
, RY/BY becomes valid. See Figure 28 for the timing
waveform.
Since the RY/BY bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor
to V
CC
.
hardware-reset bit (RESET)
When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset
state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the
RESET pulse.
During program or erase operation, if RESET is asserted to logic low, the RY/BY bit remains at logic low until
the reset operation is complete. Since this can take from 1
μ
s to 20
μ
s, the RY/BY bit can be used to sense reset
completion or the user can allow a maximum of 20
μ
s. If RESET is asserted during read mode, then the reset
operation is complete within 500 ns. See Figure 1 and Figure 2 for timing specifications.
The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying
V
SS
±
0.3 V to it. I
CC4
reads <1
μ
A typical, and 5
μ
A maximum for CMOS inputs. Standby mode can be entered
anytime, regardless of the condition of CE.
P
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