- 您现在的位置：买卖IC网 > PDF目录382635 > TMS320C241PGS 16-Bit Digital Signal Processor PDF资料下载
参数资料
| 型号： | TMS320C241PGS |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位数字信号处理器 |
| 文件页数： | 32/116页 |
| 文件大小： | 1485K |
| 代理商： | TMS320C241PGS |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt vectors (continued)
The peripheral interrupt vectors (PIVs) are stored in a table in the peripheral interrupt expansion controller. They
can either be hard-coded (potentially ROM), or register locations (RAM), which are programmed by the reset
service routine. The PIVs are all implemented as hard-coded values on the ’F243/’F241 devices, according to
Table 10, column 5.
phantom interrupt vector
The phantom interrupt vector is an interrupt system integrity feature. If the CPU’s interrupt acknowledge is
asserted, but there is no associated peripheral interrupt request asserted, the phantom vector is used so that
this fault is handled in a controlled manner. One way the phantom interrupt vector could be required is if the CPU
executes a software interrupt instruction with an argument corresponding to a peripheral interrupt (usually
INT1–INT6). The other way would be if a peripheral made an interrupt request, but its interrupt request flag was
cleared by software before the CPU acknowledged the request. In this case, there may be no peripheral
interrupt request asserted to the interrupt controller, so the controller would not know which peripheral interrupt
vector to load into the PIVR. In these situations, the phantom interrupt vector is loaded into the PIVR in lieu of
a peripheral interrupt vector.
software hierarchy
There are two levels of interrupt service routine hierarchy: the General Interrupt Service Routine (GISR), and
the Event-Specific Interrupt Service Routine (SISR). There is one GISR for each maskable prioritized request
(INT) to the CPU. This can perform necessary context saves before it fetches the PIV from the PIVR. This PIV
value is used to generate a branch to the SISR. There is one SISR for every interrupt request from a peripheral
to the interrupt controller. The SISR performs the actions required in response to the peripheral interrupt
request.
nonmaskable interrupts
The PIE controller does not support expansion of nonmaskable interrupts. This is because an ISR must read
the peripheral interrupt vector from the PIVR before interrupts are re-enabled. All interrupts are automatically
disabled when any of the INT1 – INT6 interrupts are serviced. If the PIVR is not read before interrupts are
re-enabled, another interrupt would be acknowledged and a new peripheral interrupt vector would be loaded
into the PIVR, causing permanent loss of the original peripheral interrupt vector. Since, by their very nature,
nonmaskable interrupts cannot be masked, they cannot be included in the interrupt expansion controller
because they could cause the loss of peripheral interrupt vectors.
interrupt operation sequence
1.
An interrupt-generating event occurs in a peripheral. The interrupt flag (IF) bit corresponding to that event
is set in a register in the peripheral. If the appropriate interrupt enable (IE) bit is set, the peripheral generates
an interrupt request to the PIE controller by asserting its PIRQ. If the interrupt is not enabled in the peripheral
register, the IF remains set until cleared by software. If the interrupt is enabled at a later time, and the
interrupt flag is still set, the PIRQ will immediately be asserted. The interrupt flag (IF) in the peripheral
register should be cleared by software only. If the IF bit is not cleared after the respective interrupt service,
future interrupts will not be recognized.
2.
If no unacknowledged CPU interrupt request of the same priority level has previously been sent, the
peripheral interrupt request, PIRQ, causes the PIE controller to generate a CPU interrupt request pulse.
This pulse is active low for 2 CPU clock cycles.
3.
The interrupt request to the CPU sets the corresponding flag in the CPU’s interrupt flag register, IFR. If the
CPU interrupt has been enabled (by setting the appropriate bit in the CPU’s Interrupt Mask Register, IMR),
the CPU stops what it is doing. It then masks all other maskable interrupts by setting the INTM bit, saves
some context, clears the respective IFR bit, and starts executing the General Interrupt Service Routine
(GISR) for that interrupt priority level. The CPU generates an interrupt acknowledge automatically, which
is accompanied by a value on the Program Address Bus (PAB) that corresponds to the interrupt priority level
being responded to. These values are shown in Table 10, column 3.
相关PDF资料 |
PDF描述 |
|---|---|
| TMS320F241FNQ | 16-Bit Digital Signal Processor |
| TMS320F241PGQ | 16-Bit Digital Signal Processor |
| TMS320F243PGEQ | 16-Bit Digital Signal Processor |
| TMS320F243PGES | 16-Bit Digital Signal Processor |
| TMS320C3X | 32-Bit Digital Signal Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TMS320C242 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FN | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FNA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242FNS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242PG | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLER |
发布紧急采购，3分钟左右您将得到回复。