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参数资料
| 型号： | TMS320C241PGS |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位数字信号处理器 |
| 文件页数： | 60/116页 |
| 文件大小： | 1485K |
| 代理商： | TMS320C241PGS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CAN configuration mode (continued)
The CAN module must be initialized before activation. This is only possible if the module is in configuration
mode. The configuration mode is set by programming the CCR bit of the MCR register with “1”. Only if the status
bit CCE (GSR.4) confirms the request by getting “1”, the initialization can be performed. Afterwards, the bit
configuration registers can be written. The module is activated again by programming the control bit CCR with
zero. After a hardware reset, the configuration mode is active.
CAN power-down mode (PDM)
The CAN peripheral’s own low-power mode must be requested before a device low-power mode is entered by
executing the IDLE instruction, if the device low-power mode is going to shut off the peripheral clocks.
Before the CPU enters its IDLE mode to enter the device low-power mode to potentially shut off ALL device
clocks, it must first request a CAN peripheral power-down by writing a “1” to the PDR bit in MCR. If the module
is transmitting a message when PDR is set, the transmission is continued until a successful transmission, a lost
arbitration, or an error condition on the CAN bus line occurs. Then, the PDA is asserted. Therefore, the module
causes no error condition on the CAN bus line. When the module is ready to enter power-down mode, the status
bit PDA is set. The CPU must then poll the PDA bit in GSR, and only enter IDLE after PDA is set.
On exiting the power-down mode, the PDR flag in the MCR must be cleared by software or is cleared
automatically if the WUBA bit in MCR is set and if there is any bus activity on the CAN bus line. When detecting
a dominant signal on the CAN bus, the wakeup interrupt flag WUIF (CAN_IFR.3) is asserted. The power-down
mode is exited as soon as the clock is switched on. There is no internal filtering for the CAN bus line.
The automatic wakeup on bus activity can be enabled or disabled by setting the configuration bit WUBA
(MCR.9). If there is any activity on the CAN bus line, the module begins its power up sequence. The module
waits until detecting 11 consecutive recessive bits on the CANRX pin and goes to bus active afterwards. The
first message, which initiates the bus activity, cannotbe received.
When WUBA is enabled, the error interrupt WUIF is asserted automatically to the PIE controller, which handles
it as a wakeup interrupt and restart the device clocks if they are stopped.
After leaving the sleep mode with a wakeup, the PDR and PDA bits (MCR.11 and GSR.3, respectively) are
cleared. The CAN error counters remain unchanged.
watchdog (WD) timer module
The ’F243/’F241 devices include a watchdog (WD) timer module. The WD function of this module monitors
software and hardware operation by generating a system reset if it is not periodically serviced by software by
having the correct key written. The WD timer operates independently of the CPU and is always enabled. It does
not need any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest
WD timer rate available (6.55 ms for a 39062.5-Hz WDCLK signal). As soon as reset is released internally, the
CPU starts executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset,
WD setup should occur early in the power-up sequence. See Figure 15 for a block diagram of the WD module.
The WD module features include the following:
WD Timer
–
Seven different WD overflow rates ranging from 6.55 ms to 1 s
–
A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
–
WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
Automatic activation of the WD timer, once system reset is released
–
Three WD control registers located in control register frame beginning at address 7020h.
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte is read
as zeros. Writing to the upper byte has no effect.
Figure 15 shows the WD block diagram. Table 19 shows the different WD overflow (timeout) selections.
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相关代理商/技术参数 |
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| TMS320C242 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FN | 制造商:TI 制造商全称:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242FNA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242FNS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Digital Signal Processor |
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