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| 型号： | TMS320C6205ZHK200 |
| 厂商： | Texas Instruments |
| 文件页数： | 60/73页 |
| 文件大小： | 0K |
| 描述： | IC DSP FIXED POINT HP 288-BGA |
| 标准包装： | 1 |
| 系列： | TMS320C62x |
| 类型： | 定点 |
| 接口： | McBSP，PCI |
| 时钟速率： | 200MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.50V |
| 工作温度： | 0°C ~ 90°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 288-LFBGA |
| 供应商设备封装： | 288-BGA Microstar（16x16） |
| 包装： | 托盘 |
| 其它名称： | 296-19385 |
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TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 38)
200
NO.
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
12
2 3P
ns
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
4
5 + 6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1 (see Figure 38)
200
NO.
PARAMETER
MASTER§
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high
H 2
H + 3
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
T 2
T + 1
ns
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
2
4
3P + 4
5P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
2
4
3P + 3
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L 2
L + 4
2P + 2
4P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
7
6
2
1
CLKX
FSX
DX
DR
Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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相关代理商/技术参数 |
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|---|---|
| TMS320C6205ZHKA200 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMS320C6211 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMS320C6211_08 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSORS |
| TMS320C6211B | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMS320C6211BGFN150 | 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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