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参数资料
型号： TMS320C6415TBZLZ8
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 64-BIT, 75.18 MHz, OTHER DSP, PBGA532
封装： 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532
文件页数： 22/142页
文件大小： 2106K
代理商： TMS320C6415TBZLZ8
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
118
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP (see Figure 51)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1.4
10
ns
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
4P or 6.67§#
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C 1||
C + 1||
ns
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
2.1
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
1.7
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
1.7
9
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
CLKX int
3.9
4
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
CLKX ext
2
9
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
3.9 + D1
k
4 + D2
k
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
2.0 + D1
k
9 + D2
k
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid
FSX int
2.3 + D1h
5.6 + D2h
ns
14
td(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1h
9 + D2h
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
# Use whichever value is greater.
|| C = H or L
S =
sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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