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| 型号： | TMS320C6712GLS100 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定点数字信号处理器 |
| 文件页数： | 37/70页 |
| 文件大小： | 1050K |
| 代理商： | TMS320C6712GLS100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
§
(see Figure 15
Figure 18)
NO.
200
UNIT
MIN
1.5
3.5
MAX
3
4
6
7
t
su(EDV-AREH)
t
h(AREH-EDV)
t
su(ARDYH-AREL)
t
h(AREL-ARDYH)
t
su(ARDYL-AREL)
t
h(AREL-ARDYL)
t
w(ARDYH)
t
su(ARDYH-AWEL)
t
h(AWEL-ARDYH)
t
su(ARDYL-AWEL)
t
h(AWEL-ARDYL)
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
Setup time, ARDY high before ARE low
Hold time, ARDY high after ARE low
ns
ns
ns
ns
[(RST
3) * P
6]
(RST
3) * P + 3
9
10
Setup time, ARDY low before ARE low
Hold time, ARDY low after ARE low
[(RST
3) * P
6]
(RST
3) * P + 3
ns
ns
11
Pulse width, ARDY high
2P
ns
15
16
Setup time, ARDY high before AWE low
Hold time, ARDY high after AWE low
[(WST
3) * P
6]
(WST
3) * P + 3
ns
ns
18
19
Setup time, ARDY low before AWE low
Hold time, ARDY low after AWE low
[(WST
3) * P
6]
(WST
3) * P + 3
ns
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous memory
cycles
§#
(see Figure 15
Figure 18)
NO.
PARAMETER
200
UNIT
MIN
TYP
MAX
1
2
5
t
osu(SELV-AREL)
t
oh(AREH-SELIV)
t
w(AREL)
t
d(ARDYH-AREH)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
w(AWEL)
t
d(ARDYH-AWEH)
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Pulse width, ARE low
RS * P
2
RH * P
2
ns
ns
ns
RST * P
8
12
13
14
Delay time, ARDY high to ARE high
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Pulse width, AWE low
3P
4P + 5
ns
ns
ns
ns
WS * P
2
WH * P
2
WST * P
17
Delay time, ARDY high to AWE high
3P
4P + 5
ns
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
#
Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
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