参数资料
型号: TMX320F28069UPFPA
厂商: Texas Instruments
文件页数: 152/174页
文件大小: 0K
描述: IC MCU 32BIT 128KB FLASH 80HTQFP
产品培训模块: ControlSUITE
Piccolo F2806x
标准包装: 1
系列: TMS320F2806x, Piccolo™, C2000™
核心处理器: C28x
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 40
程序存储器容量: 256KB(128K x 16)
程序存储器类型: 闪存
RAM 容量: 50K x 16
电压 - 电源 (Vcc/Vdd): 1.71 V ~ 1.995 V
数据转换器: A/D 12x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP 裸露焊盘
包装: 托盘
其它名称: 296-30085
TMX320F28069UPFPA-ND
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.9
Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurently. The following is
a list of major features of the CLA.
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
Complete bus architecture:
Program address bus and program data bus
Data address bus, data read bus, and data write bus
Independent eight-stage pipeline.
12-bit program counter (MPC)
Four 32-bit result registers (MR0–MR3)
Two 16-bit auxillary registers (MAR0, MAR1)
Status register (MSTF)
Instruction set includes:
IEEE single-precision (32-bit) floating-point math operations
Floating-point math with parallel load or store
Floating-point multiply with parallel add or subtract
1/X and 1/sqrt(X) estimations
Data type conversions.
Conditional branch and call
Data load and store operations
The CLA program code can consist of up to eight tasks or interrupt service routines.
The start address of each task is specified by the MVECT registers.
No limit on task size as long as the tasks fit within the CLA program memory space.
One task is serviced at a time through to completion. There is no nesting of tasks.
Upon task completion, a task-specific interrupt is flagged within the PIE.
When a task finishes, the next highest-priority pending task is automatically started.
Task trigger mechanisms:
C28x CPU via the IACK instruction
Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
Task1: ADCINT1 or EPWM1_INT
Task2: ADCINT2 or EPWM2_INT
Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT.
Memory and Shared Peripherals:
Two dedicated message RAMs for communication between the CLA and the main CPU.
The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
The CLA has direct access to the ADC Result registers, comparator registers, and the eCAP,
eQEP, and ePWM+HRPWM registers.
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
79
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