TMS320LF2407A,
TMS320LF2406A,
TMS320LF2403A,
TMS320LF2402A
TMS320LC2406A,
TMS320LC2404A,
TMS320LC2403A,
TMS320LC2402A
DSP
CONTROLLERS
SPRS145K
JUL
Y
2000
REVISED
AUGUST
2005
POST
OFFICE
BOX
1443
HOUST
ON,
TEXAS
77251
1443
91
SPI MASTER MODE TIMING PARAMETERS
SPI master mode timing information is listed in the following tables.
SPI master mode external timing parameters (clock phase = 0) (see Figure 41)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
1
tc(SPC)M
Cycle time, SPICLK
4tc(CO)
128tc(CO)
5tc(CO)
127tc(CO)
ns
2§
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M10
0.5tc(SPC)M
0.5tc(SPC)M0.5tc(CO)10
0.5tc(SPC)M 0.5tc(CO)
ns
2§
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M10
0.5tc(SPC)M
0.5tc(SPC)M0.5tc(CO)10
0.5tc(SPC)M 0.5tc(CO)
ns
3§
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M10
0.5tc(SPC)M
0.5tc(SPC)M+0.5tc(CO)10
0.5tc(SPC)M + 0.5tc(CO)
ns
3§
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M10
0.5tc(SPC)M
0.5tc(SPC)M+0.5tc(CO)10
0.5tc(SPC)M + 0.5tc(CO)
ns
4§
td(SPCH-SIMO)M
Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0)
10
10
10
10
ns
4§
td(SPCL-SIMO)M
Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1)
10
10
10
10
ns
5§
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity =0)
0.5tc(SPC)M10
0.5tc(SPC)M+0.5tc(CO)10
ns
5§
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity =1)
0.5tc(SPC)M10
0.5tc(SPC)M+0.5tc(CO)10
ns
8§
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
0
ns
8§
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
0
ns
9§
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M10
0.5tc(SPC)M 0.5tc(CO)10
ns
9§
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25tc(SPC)M10
0.5tc(SPC)M 0.5tc(CO)10
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/CLKOUT = tc(CO)
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).