Rev. 1.1
51
C8051F410/1/2/3
5.
12-Bit ADC (ADC0)
The ADC0 subsystem for the C8051F41x consists of an analog multiplexer (AMUX0) with 27 total input
selections, and a 200 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold,
programmable window detector, and hardware accumulator. The ADC0 subsystem has a special
Burst
Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low
power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in
Figure 5.1.ADC0 inputs are single-ended and may be configured to measure P0.0-P2.7, the Temperature Sensor out-
put, VDD, or GND with respect to GND. ADC0 is enabled when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shut-
down when AD0EN is logic 0 and no Burst Mode conversions are taking place.
12-Bit
SAR
ADC
RE
F
FCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0LJS
T
AD
0
WIN
T
AD0B
U
S
Y
AD
0IN
T
BURS
T
E
N
AD0
E
N
Timer 2 Overflow
Start
Conversion
00
AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
27-to-1
AMUX
VDD
P0.0
P0.7
01
10
11
CNVSTR Input
Window
Compare
Logic
P1.0
P1.7
Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
ADC0MX
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
P2.0
P2.3-P2.6 available on
‘F410/2
P2.7
GND
Temp Sensor
ADC0CF
AD0RPT
0
AD0RPT
1
AD0S
C0
AD0S
C1
AD0S
C2
AD0S
C3
AD0S
C4
ADC0TK
AD0PWR3
AD0PWR2
AD0PWR1
AD0PWR0
AD0T
M
1
AD0T
M
0
AD0
T
K1
AD0
T
K0
Burst Mode
Logic
AD0PO
S
T
AD0P
R
E
AD0
T
M
1:0
Accumulator
Start
Conversion
Burst Mode
Oscillator
25 MHz Max
SYSCLK
FC
LK
Figure 5.1. ADC0 Functional Block Diagram
5.1.
Analog Multiplexer
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0-P2.7,
the on-chip temperature sensor, the core power supply (VDD), or ground (GND). ADC0 is single-ended
and all signals measured are with respect to GND. The ADC0 input channels are selected using the
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2) and write a ‘1’ in the corresponding
Port Latch register Pn (for n = 0,1,2). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding
configuration details.