Rev. 1.1
185
C8051F410/1/2/3
Internal Register Definition 20.5. RTC0XCN: smaRTClock Oscillator Control
Bit 7:
AGCEN: Crystal Oscillator Automatic Gain Control Enable Bit (Crystal Mode only).
0: Automatic Gain Control disabled.
1: Automatic Gain Control enabled.
Bit 6:
XMODE: smaRTClock Mode Select Bit.
This bit selects whether smaRTClock will be used with or without a crystal.
0: smaRTClock is configured to Self-Oscillate Mode.
1: smaRTClock is configured to Crystal Mode.
Bit 5:
BIASX2: smaRTClock Bias Double Enable Bit.
0: smaRTClock Bias Current Doubling is disabled.
1: smaRTClock Bias Current Doubling is enabled.
Bit 4:
CLKVLD: smaRTClock Clock Valid Bit.
Set by hardware when the smaRTClock crystal oscillator is nearly stable. This bit always
reads 1b when smaRTClock is used in Self-Oscillate Mode (XMODE = 0). This bit should be
checked at least 1 ms after enabling the smaRTClock oscillator circuit and should not be
used for an oscillator fail detect (use OSCFAIL in RTC0CN instead).
Bits 3–1: UNUSED. Read = 000b. Write = don’t care.
Bit 0:
VBATEN: smaRTClock VBAT Indicator.
Note: This bit always reads 1b when smaRTClock is disabled (RTC0EN = 0).
For smaRTClock enabled (RTC0EN = 1):
0: smaRTClock is powered from VDD.
1: smaRTClock is powered from the VRTC-BACKUP supply.
R/W
R
Reset Value
AGCEN
XMODE
BIASX2
CLKVLD
-
VBATEN
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
smaRTClock
Address:
Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT.
0x07
20.3. smaRTClock Timer and Alarm Function
The smaRTClock timer is a 47-bit counter that, when running (RTC0TR = 1), is incremented every RTC-
CLK cycle. The timer has an alarm function that can be set to generate an interrupt, reset the MCU, or
release the internal oscillator from Suspend Mode at a specific time.
20.3.1. Setting and Reading the smaRTClock Timer Value
The 47-bit smaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
Step 1. Write the desired 47-bit set value to the CAPTUREn registers (the LSB of CAPTURE0 is
not used).
Step 2. Write ‘1’ to RTC0SET. This will transfer the contents of the CAPTUREn registers to the
timer.
Step 3. Operation is complete when RTC0SET is cleared to ‘0’ by hardware.