参数资料
型号: TPA0172PWP
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频控制
英文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO24
封装: GREEN, PLASTIC, HTSSOP-24
文件页数: 17/36页
文件大小: 885K
代理商: TPA0172PWP
TPA0172
2W STEREO AUDIO POWER AMPLIFIER
WITH I2C BUS
SLOS327C AUGUST 2000 REVISED MAY 2001
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
shutdown modes
The TPA0172 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal
should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the
outputs to mute and the amplifier to enter a low-current state (IDD = 15 A). SHUTDOWN should never be left
unconnected because amplifier operation would be unpredictable.
The external SHUTDOWN pin may also be disabled and its function controlled through the I2C interface. Refer
to the I2C interface section.
I2C interface
The I2C interface is used to access the internal registers of the TPA0172. This two pin interface consists of one
clock line (SCL) and one serial data line (SDA). The basic I2C access cycles are shown in Figure 26.
The basic access cycle consists of the following:
D A start condition
D A slave address cycle
D Any number of data cycles
D A stop condition
Start Condition (S)
Stop Condition (P)
SDA
SCL
Figure 26. I2C Start and Stop Conditions
The start and stop conditions are shown in Figure 26. The high-to-low transition of SDA while SCL is high,
defines the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. Each
cycle, data, or address consists of 8 bits of serial data followed by one acknowledge bit generated by the
receiving device. Thus, each data/address cycle contains nine bits as shown in Figure 27.
SCL
SDA
MSB
Slave Address
Data
Stop
1
2
3
4
56
78
9
1
23
4
5
67
8
9
Acknowledge
Figure 27. I2C Access Cycles
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