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参数资料
| 型号： | TPA2016D2RTJT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 2.8 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC20 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, QFN-20 |
| 文件页数： | 14/38页 |
| 文件大小： | 1216K |
| 代理商： | TPA2016D2RTJT |
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MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
Register
SINGLE-BYTE READ
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
DataByte
D7
D6
D1
D0 ACK
I2CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/W
A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6
A0
ACK
Acknowledge
I2CDeviceAddressand
Read/WriteBit
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
www.ti.com........................................................................................................................................................ SLOS524D – JUNE 2008 – REVISED AUGUST 2009
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA2016D2 as shown in Figure 38. After receiving each data byte,
the TPA2016D2 responds with an acknowledge bit.
Figure 38. Multiple-Byte Write Transfer
As Figure 39 shows, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a
read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a '0'.
After receiving the TPA2016D2 address and the read/write bit, the TPA2016D2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA2016D2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2016D2 address and
the read/write bit again. This time the read/write bit is set to '1', indicating a read transfer. Next, the TPA2016D2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 39. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA2016D2 to the master device as shown in Figure 40. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 40. Multiple-Byte Read Transfer
Copyright 2008–2009, Texas Instruments Incorporated
21
Product Folder Link(s): TPA2016D2
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