参数资料
型号: TPA5051RSATG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC16
封装: 4 X 4 MM, GREEN, PLASTIC, QFN-16
文件页数: 4/23页
文件大小: 812K
代理商: TPA5051RSATG4
www.ti.com
COMPLETE UPDATE REGISTER (0x08, 0x10)
APPLICATION EXAMPLES
Connecting Two Devices in Series to Increase the Delay
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
2kW
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
BCLK1
LRCLK1
DATA1
DATA2
BCLK2
LRCLK2
DATA_OUT1
DATA_OUT2
DATA_OUT1
DATA_OUT2
VDD
GND
0.1 F
m
VDD
GND
0.1 F
m
ADD2
ADD1
ADD0
SCLK
SDA
ADD2
ADD1
ADD0
SDA
SCL
SCLK
Audio
Processor
SDA
SCL
Audio
Amplifier
SLOS497A – JUNE 2006 – REVISED JULY 2006
Since the audio delay values are divided among several registers, it is likely that multiple writes would be
necessary to configure the device. This may cause interruptions in the audio stream and unwanted pops and
clicks might occur as register data is passed to delay functional block.
To avoid this from happening, the Complete Update register is used to transfer the user settings from the
register file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to
35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35
samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data have
passed.
The Complete Update register must also be used when either the stream type is changed or the RJ packet
length is changed. If a complete update command is not issued, the changes will not take effect.
Note that the individual channels can be muted using the upper bits of the Control Registers without writing to
the Complete Update registers.
Table 7. Complete Update Registers (0x08, 0x10)(1)
D7–D1
D0
FUNCTION
X
0
No data from the register settings is passed to the delay block.
X
1
Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
(1)
Default values are in bold.
It is sometimes desirable to increase the delay time beyond which one device can provide. In such cases,
several TPA5051 devices can be placed in series to increase the delay. A maximum of eight devices can be
placed in series. This is because each device has eight I2 address settings. Under no circumstances should two
TPA5051 devices share the same I2S address. See Figure 11.
Figure 11. Two Devices Connected in Series
12
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