Input Capacitor
Load Capacitor
C v
I
(PD)
180
10 mA
(2)
Transient Suppressor
Layout
data sheet
SLVS525B – APRIL 2004 – REVISED APRIL 2008............................................................................................................................................................ www.ti.com
The IEEE 802.3af requires a PD input capacitance between 0.05 F and 0.12
F during detection. This capacitor
should be located directly adjacent to the TPS2375 as shown in
Figure 1. A 100-V, 10%, X7R ceramic capacitor
meets the specification over a wide temperature range.
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5
F. It is
permissible to have a much larger load capacitor, and the TPS2375 can charge in excess of 470 F before
thermal issues become a problem. However, if the load capacitor is too large, the PD design may violate IEEE
802.3af requirements.
If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE caused by
failure to meet the MPS. This is caused by having a long input current dropout due to a drop in input voltage with
a large capacitance-to-load ratio. The standard gives
Equation 2:where C is the bulk capacitance in
F and I
(PD) is the PD load current in mA.
A particular design may have a tendency to cause ringing at the RTN pin during startup, inadvertent hot-plugs of
the PoE input, or plugging in a wall adapter. It is recommended that a minimum value of 1 F be used at the
output of the TPS2375 if downstream filtering prevents placing the larger bulk capacitor right on the output. When
using ORing option 2, it is recommended that a large capacitor such as a 22
F be placed across the TPS2375
output.
Voltage transients on the TPS2375 can be caused by connecting or disconnecting the PD, or by other
environmental conditions like ESD. The TPS2375 is specified to operate with absolute maximum voltages
V(VDD-VSS) and V(RTN-VSS) of 100 V. A transient voltage suppressor, such as the SMAJ58A, should be installed
after the bridge and across the TPS2375 input as shown in
Figure 1. Various configurations of output filters and
the insertion of local power sources across either the TPS2375 input or output have the potential to cause
stresses outside the absolute maximum ratings of the device. Designers should be aware of this possibility and
account for it in their circuit designs. For example, use adequate capacitance across the output to limit the
magnitude of voltage ringing caused by downstream filters. Plugging an external power source across the output
may cause ESD-like events. Some form of protection should be considered based on a study of the specific
waveforms seen in an application circuit.
The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set of
recommendations include:
1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45
→ Ethernet
transformer
→ diode bridges → TVS and 0.1-
F capacitor → TPS2375 → output capacitor.
2. There should not be any crossovers of signals from one part of the flow to another.
3. All leads should be as short as possible with wide power traces and paired signal and return.
4. Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
5. The TPS2375 should be over a local ground plane or fill area referenced to VSS to aid high-speed operation.
6. Large SMT component pads should be used on power dissipating devices such as the diodes and the
TPS2375.
Use of added copper on local power and ground to help the PCB spread and dissipate the heat is recommended.
Pin 4 of the TPS2375 has the lowest thermal resistance to the die.
16
Copyright 2004–2008, Texas Instruments Incorporated