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参数资料
型号： TPS3824-30QDBVRQ1
厂商： TEXAS INSTRUMENTS INC
元件分类： 电源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO5
封装： GREEN, PLASTIC, SOT-23, 5 PIN
文件页数： 13/15页
文件大小： 276K
代理商： TPS3824-30QDBVRQ1
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
SGLS143B DECEMBER 2002 REVISED JUNE 2008
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH(AV)
Average high-level input current
WDI
WDI = VDD,
time average (dc = 88%)
120
IIL(AV)
Average low-level input current
WDI
WDI = 0.3 V, VDD = 5.5 V
time average (dc = 12%)
15
WDI
WDI = VDD
140
190
μA
IIH
High-level input current
MR
MR = VDD × 0.7,
VDD = 5.5 V
40
60
μA
I
Low level input current
WDI
WDI = 0.3 V, VDD = 5.5 V
140
190
IIL
Low-level input current
MR
MR = 0.3 V, VDD = 5.5 V
110
160
TPS382x-25
I
Output short-circuit current
RESET
TPS382x-30
VDD = VIT, max + 0.2 V,
400
A
IOS
Output short circuit current
(see Note 4)
RESET
TPS382x-33
VDD = VIT, max + 0.2 V,
VO = 0 V
400
μA
TPS382x-50
O
800
IDD
Supply current
WDI and MR unconnected,
Outputs unconnected
15
25
μA
Internal pullup resistor at MR
52
k
Ω
Ci
Input capacitance at MR, WDI
VI = 0 V to 5.5 V
5
pF
NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a
μP bidirectional reset pin.
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
at VDD
VDD = VIT + 0.2 V,
VDD = VIT- - 0.2 V
6
μs
tw
Pulse width
at MR
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
1
μs
w
at WDI
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
100
ns
switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Watchdog time out
TPS3820
VDD ≥ VIT + 0.2 V,
112
200
310
ms
ttout
Watchdog time out
TPS3823/4/8
VDD ≥ VIT + 0.2 V,
See Timing Diagram
0.9
1.6
2.5
s
t
Delay time
TPS3820
VDD ≥ VIT + 0.2 V,
15
25
37
ms
td
Delay time
TPS3823/4/5/8
VDD ≥ VIT + 0.2 V,
See timing diagram
120
200
300
ms
tPHL
Propagation (delay) time,
high-to-low-level output
MR to RESET delay
(TPS3820/3/5/8)
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
0.1
μs
tPHL
high-to-low-level output
VDD to RESET delay
VIL = VIT- - 0.2 V,
VIH = VIT- + 0.2 V
25
μs
tPLH
Propagation (delay) time,
low to high level output
MR to RESET delay (TPS3824/5)
VDD ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
0.1
μs
tPLH
low-to-high-level output
VDD to RESET delay (TPS3824/5)
VIL = VIT- - 0.2 V,
VIH = VIT- + 0.2 V
25
μs
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