参数资料
型号: TPS40021PWP
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 0.01 A SWITCHING CONTROLLER, 1100 kHz SWITCHING FREQ-MAX, PDSO16
封装: GREEN, PLASTIC, HTSSOP-16
文件页数: 7/36页
文件大小: 724K
代理商: TPS40021PWP
TPS40020
TPS40021
SLUS535D MARCH 2003 REVISED JULY 2007
www.ti.com
15
APPLICATION INFORMATION
Transient Comparators and Power Good
The TPS4002x makes use of a separate pin, OSNS, to monitor output voltage for these two functions. In normal
operation, OSNS is connected to the output via a resistor divider. It is important to make this divider the same
ratio as the divider for the feedback network so that in normal operation the voltage at OSNS is the same as
the voltage at FB, 0.69 V nominal.
The PWRGD pin is an open drain output that is pulled low when the voltage at OSNS falls outside 0.69 V
±4.6%
(approximately). A delay has been purposely built into the PWRGD pin pulling low in response to an out of band
voltage on OSNS, to minimize the need for filtering the signal in the event of a noise glitch causing a brief out
of band OSNS voltage. The PWRGD signal returns to high when the OSNS signal returns to approximately
±1%
of nominal (0.69 V
±1%).
The transient comparators override the conventional voltage control loop when the output voltage exceeds a
±4.6% window. If the output transition is high (i.e. load steps down from 90% load to 10 % load) then the HDRV
gate drive is terminated, 0% duty cycle, the LDRV gate drive is turned on to sink output current until VOUT returns
to within 1% of nominal. Conversely when VOUT drops outside the window (i.e. step load increases from 10%
load to 90% load) HDRV increases to maximum duty cycle until VOUT returns to within 1% of nominal. (See
Figure 7.)
During start-up, the transient comparators control the state of PWRGD as previously described. However, the
operation of the gate drive outputs is not affected. (See Figure 8)
The transient comparators provide an improvement in load transient recovery time if used properly. In some
situations, recovery time may be one half of the time required without transient comparators. Keep in mind that
the transient comparator concept is a double-edged sword. While they provide improved transient recovery
time, they can also lead to instability if incorrectly applied. For proper functionality, design a feedback loop for
the converter that places the closed loop unity gain frequency at least five times higher than the 0 dB frequency
of the output L-C filter. If not, the feedback loop cannot respond to the ring of the L-C on a transient event. The
ring is likely to be large enough to disturb the transient comparators and the result is a power oscillator. Another
helpful action is to ground the feedback loop divider and the OSNS divider at the SGND pin. Make sure both
dividers measure the same physical location on the output bus. These help avoid problems with resistive drops
at higher loads causing problems.
Connecting OSNS to VDD disables the transient comparators. This also disables the PWRGD function.
Alternatively, OSNS and FB can be tied together. This connection allows a proper PWRGD at startup, though
transient performance diminishes.
UDG03181
98 % Duty Cycle
0 % Duty Cycle
98 % Duty Cycle
0 % Duty Cycle
10
s
500 n s
4.6%
1%
4.6%
1%
< 10
s
10
s
FB
PWRGD
SW
4.6%
Figure 7. Duty Cycle Waveforms
相关PDF资料
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