参数资料
型号: TPS40060PWPG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16
封装: GREEN, PLASTIC, HTSOOP-16
文件页数: 17/33页
文件大小: 750K
代理商: TPS40060PWPG4
www.ti.com
A
MOD(f) + AMOD
f
LC
f
C
2
+ 5
3.7 kHz
10 kHz
2
+ 0.68
(70)
G +
1
A
MOD(f)
+
1
0.68 +
1.46
(71)
f
Z2 +
1
2p
R1
C3 N
C3 +
1
2p
100 kW
3.7 kHz +
430 pF, choose 470 pF
(72)
f
P2 +
1
2p
R3
C3 N
R3 +
1
2p
470 pF
73.3 kHz +
4.62 kW, choose 4.64 kW
(73)
f
C +
1
2p
R1
C2
G N
C2 +
1
2p
100 kW
3.29
1.46 kHz +
109 pF, choose 100 pF
(74)
f
P1 +
1
2p
R2
C2 N
R2 +
1
2p
100 pF
73.3 kHz +
21.7 kW, choose 21.5 kW
(75)
f
Z1 +
1
2p
R2
C1 N
C1 +
1
2p
21.5 kW
3.7 kHz +
2000 pF, choose 1800 pF
(76)
R
BIAS +
0.7 V
R1
V
O * 0.7 V
+
0.7 V
100kW
3.3 V * 0.7 V
+ 26.9 kW, choose 26.7 kW
(77)
CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE
C
BPN10 +
Qg
DV
+
30 nC
0.5 +
60 nF
(78)
C
BP10V +
Q
gSR
DV
+
57 nC
0.5 +
114 nF
(79)
GATE DRIVE CONFIGURATION
SLUS543E – DECEMBER 2002 – REVISED JUNE 2006
DESIGN EXAMPLE (continued)
Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7
kHz.
The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 27.
And also from Equation 27.
Choose R1 = 100 k
The poles and zeros for a Type III network are described in Equation 25 and Equation 26.
Calculate the value of RBIAS from Equation 23 with R1 = 100 k.
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin
from Equation 8 is shown in Equation 78.
and the BP10V capacitance from Equation 9 is shown in Equation 79.
For this application, a 0.1-F capacitor was used for the BPN10V and a 1.0-F was used for the BP10V bypass
ccapacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter
specified in the design example.
Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDS voltage and low
gate threshold voltage of the Si4470, the design includes a 2-
in the gate lead of the upper MOSFET. The
resistor can be used to shape the low-to-high transition of the SWitch node and reduce the tendancy of
dv/dt-induced turn on.
24
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