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| 型号： | TPS40193DRCR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 360 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | 3 X 3 MM, GREEN, PLASTIC, SON-10 |
| 文件页数： | 16/38页 |
| 文件大小： | 707K |
| 代理商： | TPS40193DRCR |
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C
BP5 + 100
MAX Q
G1, QG2
R
VDD t
V
RVDD(max)
I
DD
+
50 mV
3 mA ) QG1, QG2
f
SW
V
CS + IL(peak)
R
DS(on)
A
MOD +
dV
OUT
dV
COMP
+
dD
V
COMP
V
IN +
dt
dV
RAMP
1
T
SW
V
IN
A
MOD +
V
IN
V
RAMP(p*p)
f
RES +
1
2p
L
C
www.ti.com
SLUS719C – MARCH 2007 – REVISED AUGUST 2010
Input Bypass Capacitor (C6)
As suggested the TPS40192/93 datasheet, select a 1.0-mF ceramic bypass capacitor for VDD.
BP5 Bypass Capacitor (C5)
The TPS40192 recommends a minimum 1.0-mF ceramic capacitance to stabilize the 5-V regulator. To limit
regulator noise to less than 10 mV, the bypass capacitor is sized by using Equation 23.
(23)
Since Q2 is larger than Q1 and Q2's total gate charge is 44 nC, a BP5 capacitor of 4.4-mF is calculated, and the
next larger standard value of 4.7 mF is selected to limit noise on the BP5 regulator.
Input Voltage Filter Resistor (R11)
VIN(min) > 6.0 V so a 0 resistor is placed in the VDD resistor location. If VIN(min) was < 6.0 V, an optional 1 to 2
series VDD resistor could be used to filter switching noise from the device. Limit the voltage drop across this
resistor to less than 50 mV.
(24)
Driving the two FETs with 23 nC and 44 nC respectively, we calculate a maximum IVDD current of 43 mA and
would select a 1-
resistor.
Short Circuit Protection (R9)
The TPS40192/93 use the negative drop across the low-side FET during the OFF time to measure the inductor
current. The voltage drop across the low-side FET is given by Equation 25.
(25)
When 8 V
≤ VIN ≤14 V, IL(peak) = 11.5 A Using the IRF7834 MOSFET, we calculate a peak voltage drop of
63.3 mV.
The TPS40192's internal temperature coefficient helps compensate for the MOSFET's RDS(on) temperature
coefficient. For this design select the short circuit protection voltage threshold of 110 mV by selecting R9 =
3.9 k
.
Feedback Compensation
Modeling the Power Stage
The DC gain of the modulator is given by Equation 26.
(26)
Since the peak-to-peak ramp voltage given in the Electrical Characteristics Table is projected from the ramp
slope over a full switching period, the modulator gain can be calculated as Equation 27.
(27)
This design finds a maximum modulator gain of 14 (23.0 dB). The L-C filter applies a double pole at the
resonance frequency described in Equation 28.
(28)
Copyright 2007–2010, Texas Instruments Incorporated
23
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