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参数资料
| 型号： | TPS40304DRCR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | 3 X 3 MM, GREEN, PLASTIC, SON-10 |
| 文件页数： | 30/31页 |
| 文件大小： | 1798K |
| 代理商： | TPS40304DRCR |
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5
4
3
2
1
6
7
8
9
10
FB
COMP PGOOD EN/SS VDD
BOOT HDRV
SW
LDRV/
OC
BP
Thermal Pad
SLUS964 – NOVEMBER 2009
www.ti.com
DEVICE INFORMATION
TERMINAL CONFIGURATION
The package is an 10-Pin SON (DRC) package. Note: The thermal pad is an electrical ground connection.
PIN FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high side N-channel MOSFET. A 100 nF capacitor (typical) must be connected
BOOT
6
I
between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 F or greater from
BP
10
O
this pin to GND.
COMP
4
O
Output of the error amplifier and connection node for loop feedback components.
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 A. The resulting voltage ramp of this pin is also used as a second non-inverting
EN/SS
2
I
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267 k
Ω resistor from this pin to BP enables
frequency spread spectrum feature.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
FB
5
I
reference voltage.
PGOOD
3
O
Open drain power good output.
HDRV
7
O
Bootstrapped gate drive output for the high side N-channel MOSFET.
Gate drive output for the low side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
LDRV/OC
9
O
is also used to determine the voltage level for OCP. An internal current source of 10 A flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1.0-F close
VDD
1
I
to the device.
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high
SW
8
O
side FET driver.
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
Thermal
connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
GND
Pad
The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.
8
Copyright 2009, Texas Instruments Incorporated
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