![](http://datasheet.mmic.net.cn/130000/TPS54073PWPRG4_datasheet_5022218/TPS54073PWPRG4_13.png)
2
LC
IN(NOM)
Z2
Z1
CO
INT
V
f
=
(18)
4
V
IN(NOM)
CO
INT
=
f
(19)
LC +
1
2p
L
OUT
C
OUT
(11)
C6 +
1
2pR1
INT
(20)
R3 +
1
p
C6
LC
(21)
R2 +
R1
0.891
V
OUT *
0.891
(12)
C8 +
1
2pR1
LC
(22)
ESR0 +
1
2pR
ESR
C
OUT
(23)
Z1 +
1
2pR3C6
(13)
Z2 +
1
2pR1C8
(14)
P1 +
1
2pR5C8
(15)
R5 +
1
2pC8
ESR
(24)
P2 +
1
2pR3C7
(16)
INT +
1
2pR1C6
(17)
C7=
1
2 R3x150000
p
(25)
www.ti.com ............................................................................................................................................................................................ SLVS547 – FEBRUARY 2005
phase margin at crossover must be greater than 45
degrees.
The
general
procedure
outlined
here
produces results consistent with these requirements
without going into great detail about the theory of loop
compensation.
For this design, one zero is placed at fLC and the
First, calculate the output filter LC corner frequency
It is important to note that these equations are only
For the design example, fLC = 5.906 kHz.
valid for the pole and zero locations as specified
The closed-loop crossover frequency should be
chosen to be greater than fLC and less than one-fifth
of the switching frequency. Also, the crossover
frequency should not exceed 100 kHz, as the error
amplifier may not provide the desired gain. For this
The first zero, fZ1 is located at one-half the output
design, a crossover frequency of 40 kHz was chosen.
filter LC corner frequency; so, R3 can be calculated
This value is chosen for comparatively wide loop
from:
bandwidth while still allowing for adequate phase
boost to insure stability.
Next, calculate the R2 resistor value for the output
The second zero, fZ2 is located at the output filter LC
corner frequency; so, C8 can be calculated from:
For any TPS54073 design, start with an R1 value of
10 k
. R2 is 14.7 k.
The first pole, fP1 is located to coincide with output
Now, the values for the compensation components
filter ESR zero frequency. This frequency is given by:
that set the poles and zeros of the compensation
network can be calculated. Assuming that R1 >> than
R5 and C6 >> C7, the pole and zero locations are
where RESR is the equivalent series resistance of the
output capacitor.
In this case, the ESR zero frequency is 48.2 kHz, and
R5 can be calculated from:
The final pole is placed at a frequency above the
closed-loop crossover frequency high enough to not
cause the phase to decrease too much at the
Additionally, there is a pole at the origin, which has
crossover frequency while still providing enough
unity gain at a frequency:
attenuation so that there is little or no gain at the
switching frequency. The fP2 pole location for this
circuit is set to 150 kHz and the last compensation
This pole is used to set the overall gain of the
component value C7 can be derived:
compensated error amplifier and determines the
closed-loop crossover frequency. Because R1 is
given as 10 k
and the nominal crossover frequency
Note that capacitors are only available in a limited
is selected as 40 kHz, the desired fINT can be
range of standard values, so the nearest standard
value has been chosen for each capacitor. The
measured closed-loop response for this design is
Copyright 2005, Texas Instruments Incorporated
13