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| 型号： | TPS54162QPWPRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | GREEN, PLASTIC, HTSSOP-20 |
| 文件页数： | 11/41页 |
| 文件大小： | 2414K |
| 代理商： | TPS54162QPWPRQ1 |
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SLVSA32C – OCTOBER 2009 – REVISED MAY 2010
Synchronization With External Clock
An external clock signal can be supplied to the device through SYNC pin (pin 3) to synchronize the internal
oscillator frequency with an external clock frequency. The synchronization input overrides the internal fixed
oscillator signal. The synchronization signal has to be valid for approximately two clock cycles before the
transition is made for synchronization with the external frequency input. If the external clock input does not
transition low or high for 32 s (typical), the system defaults to the internal clock set by the resistor connected to
the RT pin. The SYNC input can have a frequency according to Equation 8.
180 kHz < fsw < fext < 2 × fsw < 2.2 MHz
(8)
Where,
fsw = oscillator frequency determined by resistor connected to the RT pin
fext = frequency of the external clock fed through SYNC pin
For example, if the resistor connected at RT pin is selected such that the switching frequency (fsw) is 500 kHz,
then the external clock can have a frequency (fext) between 500 kHz and 1000 kHz. But, if the resistor connected
at RT pin is selected such that the switching frequency (fsw) is 1500 kHz, then the external clock can have a
frequency (fext) between 1500 kHz and 2200 kHz only.
If the external clock gets struck for less than 32 s, the NMOS switching FET is turned off and the output voltage
starts decreasing. Depending upon the load conditions, the output voltage may hit the under voltage threshold
and reset threshold before the external clock appears. The NMOS switching FET stays OFF until the external
clock appears again. If the output voltage hits the reset threshold, the RST pin is asserted low after a deglitch
time of 20 s (typical).
If the external clock gets struck for more than 32 s, the NMOS switching FET is turned off and the output
voltage starts decreasing. Under this condition the default internal oscillator clock set by RT pin overrides the
external after 32 s and the NMOS switching FET resumes switching. When the external clock appears again
(such that 180 kHz < fsw < fext < 2 × fsw < 2.2 MHz), the NMOS switching FET starts switching at the frequency
determined by the external clock.
Slew Rate Control
The slew rate of the NMOS switching FET can be set by using an external resistor (R7 in Figure 4). The range of
rise times and fall times for different values of slew resistor are shown in Figure 24 and Figure 25.
Figure 24. FET Rise Time
Figure 25. FET Fall Time
Reset
The RST pin (pin 8) is an open drain output pin used to indicate external digital devices/ loads if the device has
powered up to a programmed regulated output voltage properly. This pin is asserted low until the regulated
output voltage (VReg) exceeds the programed reset threshold (VREG_RST, see Equation 11) and the reset delay
timer (set by Cdly pin) has expired. Additionally, whenever the EN pin is low or open, RST is immediately
asserted low regardless of the output voltage. There is a reset filter timer to prevent reset being invoked due to
short negative transients on the output line. If thermal shut down occurs due to excessive thermal conditions, this
pin is asserted low when the switching FET is commanded OFF and the output falls below the reset threshold.
Copyright 2009–2010, Texas Instruments Incorporated
19
Product Folder Link(s): TPS54162-Q1
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