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| 型号： | TPS54162QPWPRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | GREEN, PLASTIC, HTSSOP-20 |
| 文件页数： | 38/41页 |
| 文件大小： | 2414K |
| 代理商： | TPS54162QPWPRQ1 |
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VIN
PH
VReg
VSENSE
BOOT
OV_TH
COMP
SS
RST_TH
NC
SYNC
LPM
EN
Rslew
NC
Cdly
RT
GND
RST
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SLVSA32C – OCTOBER 2009 – REVISED MAY 2010
www.ti.com
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
Figure 3.
TERMINAL FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
NC
1
NC
Connect to ground.
NC
2
NC
Connect to ground.
External synchronization clock input to override the internal oscillator clock. An internal pull down of
SYNC
3
I
62k
(typical) is connected to ground.
Low-power mode control using digital input signal. An internal pull down of 62k
(typical) is connected
LPM
4
I
to ground.
EN
5
I
Enable pin, internally pulled up. Must be externally pulled up or down to enable/ disable the device.
RT
6
O
External resistor to ground to program the internal oscillator frequency.
Rslew
7
O
External resistor to ground to control the slew rate of internal switching FET.
Active low, open drain reset output connected to external bias voltage through a resistor, asserted high
RST
8
O
after the device starts regulating.
Cdly
9
O
External capacitor to ground to program power on reset delay.
Ground pin, must be electrically connected to the exposed pad on the PCB for proper thermal
GND
10
O
performance.
SS
11
O
External capacitor to ground to program soft start time.
Sense input for overvoltage detection on regulated output, an external resistor network is connected
OV_TH
12
I
between VReg and ground to program the overvoltage threshold.
Sense input for undervoltage detection on regulated output, an external resistor network is connected
RST_TH
13
I
between VReg and ground to program the reset and undervoltage threshold.
VSENSE
14
I
Inverting node of error amplifier for voltage mode control.
COMP
15
O
Error amplifier output to connect external compensation components.
VReg
16
I
Internal low-side FET to load output during startup or limit overshoot.
PH
17
O
Source of the internal switching FET.
VIN
18
I
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
VIN
19
I
Unregulated input voltage. Pin 18 and pin 19 must be connected externally.
BOOT
20
O
External bootstrap capacitor to PH to drive the gate of the internal switching FET.
6
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54162-Q1
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