参数资料
型号: TPS54615PWPRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封装: GREEN, PLASTIC, HTSSOP-28
文件页数: 6/23页
文件大小: 706K
代理商: TPS54615PWPRG4
TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C AUGUST 2001 REVISED APRIL 2005
www.ti.com
14
and ripple characteristics, but with exceptional transient
response. Transient recovery times are typically in the
range of 10 s to 20 s.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately set and reset the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as Vref. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54611 TPS54616 devices are capable of
sinking current continuously until the output reaches the
regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and the
low-side FET turns on to decrease the energy in the output
inductor and consequently decrease the output current.
This process is repeated each cycle in which the current
limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. The high-side and low-side drivers are
designed with 300 mA source and sink capability to quickly
drive the power MOSFETs gates. The low-side driver is
supplied from VIN, while the high-side drive is supplied
from the BOOT pin. A bootstrap circuit uses an external
BOOT capacitor and internal 2.5- bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the
current flow through the high-side MOSFET and a
differential amplifier with preset overcurrent threshold. The
high-side MOSFET is turned off within 200 ns of reaching
the current limit threshold. A 100 ns leading edge blanking
circuit prevents false tripping of current limit. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point, and starts up
under control of the slow-start circuit.Thermal shutdown
provides protection when an overload condition is
sustained for several milliseconds. With a persistent fault
condition, the device cycles continuously: starting up by
control of the slow-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown trip point.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE falls
10% below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or
thermal shutdown is asserted. When VIN = UVLO
threshold, SS/ENA = enable threshold, and VSENSE >
90% of Vref, the open drain output of the PWRGD pin is
high. A hysteresis voltage equal to 3% of Vref and a 35-s
falling edge deglitch circuit prevent tripping of the power
good comparator due to high-frequency noise.
相关PDF资料
PDF描述
TPS54612PWPRG4 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
TPS54615PWPR 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
TPS54612PWPR 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
TPS54616PWP 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
TPS54614PWPG4 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
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