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参数资料
| 型号： | TPS54617RUVT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 660 kHz SWITCHING FREQ-MAX, QCC34 |
| 封装： | 3.50 X 7 MM, GREEN, VQFN-34 |
| 文件页数： | 4/21页 |
| 文件大小： | 852K |
| 代理商： | TPS54617RUVT |
VBIAS Regulator (VBIAS)
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
Slow-Start/Enable (SS/ENA)
Voltage Reference
Oscillator and PWM Ramp
t
d +
C
(SS)
1.2 V
5 mA
(2)
(
)
51000
4400
=
+
SW
T
F
R
(4)
t
(SS) +
C
(SS)
0.7 V
5 mA
(3)
SLVS880A – NOVEMBER 2008 – REVISED JANUARY 2009 ........................................................................................................................................... www.ti.com
The VBIAS regulator provides internal analog and
digital blocks with a stable supply voltage over
variations in junction temperature and input voltage. A
The TPS54617 incorporates an under voltage lockout
high quality, low-ESR, ceramic bypass capacitor is
circuit to keep the device disabled when the input
required on the VBIAS pin. X7R or X5R grade
voltage (VIN) is insufficient. During power up, internal
dielectrics are recommended because their values
circuits are held inactive until VIN exceeds the
are more stable over temperature. The bypass
nominal UVLO threshold voltage of 2.95 V. Once the
capacitor must be placed close to the VBIAS pin and
UVLO start threshold is reached, device start-up
returned to AGND.
begins. The device operates until VIN falls below the
nominal UVLO stop threshold of 2.8 V. Hysteresis in
External loading on VBIAS is allowed, with the
the UVLO comparator, and a 2.5-s rising and falling
caution that internal circuits require a minimum
edge deglitch circuit reduce the likelihood of shutting
VBIAS of 2.70 V, and external loads on VBIAS with
the device down due to noise on VIN.
ac
or
digital
switching
noise
may
degrade
performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
The slow-start/enable pin provides two functions.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
The voltage reference system produces a precise
exceeds the start threshold voltage of approximately
Vref signal by scaling the output of a temperature
1.2 V. When SS/ENA exceeds the enable threshold,
stable bandgap circuit. During manufacture, the
device start-up begins. The reference voltage fed to
bandgap and scaling circuits are trimmed to produce
the error amplifier is linearly ramped up from 0 V to
0.891 V at the output of the error amplifier, with the
0.891 V in 3.35 ms. Similarly, the converter output
amplifier connected as a voltage follower. The trim
voltage reaches regulation in approximately 3.35 ms.
procedure adds to the high precision regulation of the
Voltage hysteresis and a 2.5-s falling edge deglitch
TPS54617, since it cancels offset errors in the scale
circuit reduce the likelihood of triggering the enable
and error amplifier circuits.
due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
The oscillator frequency can be set to internally fixed
a low-value capacitor connected between SS/ENA
values of 350 kHz or 550 kHz using the SYNC pin as
and AGND.
a static digital input. If a different frequency of
operation is required for the application, the oscillator
Adding a capacitor to the SS/ENA pin has two effects
frequency can be externally adjusted from 280 to
on start-up. First, a delay occurs between release of
1600 kHz by connecting a resistor between the RT
the SS/ENA pin and start-up of the output. The delay
pin to ground and floating the SYNC pin. The
is proportional to the slow-start capacitor value and
switching frequency in MHz is approximated by the
lasts until the SS/ENA pin reaches the enable
following equation, where R is the resistance in Ohms
threshold. The start-up delay is approximately:
from RT to AGND:
Second, as the output becomes active, a brief
ramp-up at the internal slow-start rate may be
External
synchronization
of
the
PWM
ramp
is
observed before the externally set slow-start rate
possible over the frequency range of 330 kHz to 1600
takes
control
and
the
output
rises
at
a
rate
kHz by driving a synchronization signal into SYNC
proportional to the slow-start capacitor. The slow-start
and connecting a resistor from RT to AGND. Choose
time set by the capacitor is approximately:
a RT resistor that sets the free running frequency to
80%
of
the
synchronization
signal.
summarizes the frequency selection configurations:
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
12
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS54617
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