参数资料
型号: TPS54900PWG4
厂商: Texas Instruments
文件页数: 9/16页
文件大小: 0K
描述: IC REG BUCK ADJ .1A QUAD 16TSSOP
标准包装: 90
类型: 降压(降压)
输出类型: 可调式
输出数: 4
输出电压: 7.5 V ~ 13.1 V
输入电压: 15V
PWM 型: 电压模式
频率 - 开关: 450kHz
电流 - 输出: 100mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
供应商设备封装: 16-TSSOP
配用: 296-17304-ND - EVAL MODULE FOR XILINX FPGA
TPS54900
SLVS405 ? OCTOBER 2001
status readback
The TPS54900 is designed to monitor its output state and recognize when it has settled into regulation at its
programmed value. The open drain SDO pin reports a channel in a voltage transition or error condition (Channel
Not Ready) by returning a non-zero data value. When SDO returns a value of 00h, the channel is in regulation.
Any of the following conditions cause a channel not ready status to be reported:
D
D
D
D
D
Channel disabled
PWM duty factor outside expected range (i.e. 0% or 100% PW)
Channel in overcurrent
Channel transitioning to new target value
Over-temperature shutdown (affects all four channels)
Noise immunity circuits in the fault detector introduce a delay in the reporting of the channel status. For instance,
if a command to transition to a new target voltage is issued, the output voltage may be stable up to 250 μ s before
the detection circuit reports that the channel is ready. The minimum recommended status polling interval per
channel is 500 μ s.
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