参数资料
型号: TPS54900PWR
厂商: Texas Instruments
文件页数: 3/16页
文件大小: 0K
描述: IC REG BUCK ADJ .1A QUAD 16TSSOP
标准包装: 2,000
类型: 降压(降压)
输出类型: 可调式
输出数: 4
输出电压: 7.5 V ~ 13.1 V
输入电压: 15V
PWM 型: 电压模式
频率 - 开关: 450kHz
电流 - 输出: 100mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
供应商设备封装: 16-TSSOP
配用: 296-17304-ND - EVAL MODULE FOR XILINX FPGA
TPS54900
SLVS405 ? OCTOBER 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE
Enable threshold
Disable threshold
2.0
0.8
V
V
Bypass threshold
Relative to VIN
?1.4
?0.5
V
CBS
Logic high threshold
Logic low threshold
OVERCURRENT LIMIT
2.0
0.8
V
V
I(th?OCL)
t(OCL)
OCL trip threshold
OCL hiccup time
Channel settled after change of voltage code or EN
asserted
f(sync) = 552 kHz (see Note 2)
250
170
450
750
360
mA
ms
PMOS FET SWITCH
rDS(on)
ON resistance
Id = 0.1A
0.8
1.4
?
TRANSITION TIME
td(EN)
tTLH
tTHL
Enable delay time
Low?high transition time, VO
High?low transition time, VO
7.5 < VO < 15, time from EN > VIH to
Channel status word = 00H
Command from 7.5 V to bypass,
VIN = 15.0 V
Command from bypass to 7.5 V,
175 ? load with VIN = 15.0 V
9
4
4
ms
ms
ms
THERMAL SHUTDOWN
T(OTP)
T(hys)
Over temperature trip point, TJ
Hysteresis temperature
Junction temperature exceeds T(OTP)
150
10
° C
° C
SERIAL PORT
tsu
th
tc(SFS)
VOL(SDO)
Setup time, SDIN, SFS
Hold time, SDIN, SFS
Cycle time, SFS
Output low, SDO
Inputs valid before SCLK falling edge (see Note 2)
Inputs held after SCLK falling edge (see Note 2)
minimum time between commands (see Note 2)
I(sink SDO) = 0.5 mA (see Note 2)
20
5
18
0.4
ns
ns
SCLK
V
td(SCLK)
Ilkg
Delay time, SDO
Off-state leakage current, SDO
SCLK rising to SDO valid (see Note 2)
SDO = 3.3 V (see Note 2)
0
?1
15
1
ns
μ A
VIL
VIH
Input low voltage
Input high voltage
See Note 2
See Note 2
2.3
0.7
V
V
NOTE 2: Ensured by design
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