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参数资料
| 型号： | TPS54900PWR |
| 厂商： | Texas Instruments |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ .1A QUAD 16TSSOP |
| 标准包装： | 2,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 4 |
| 输出电压： | 7.5 V ~ 13.1 V |
| 输入电压： | 15V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 450kHz |
| 电流 - 输出： | 100mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP |
| 配用： | 296-17304-ND - EVAL MODULE FOR XILINX FPGA |
TPS54900
SLVS405 ? OCTOBER 2001
detailed description
reference system/voltage divider and multiplexer
The reference system consists of a band-gap circuit, four digital to analog converter outputs (DACs), and
smoothing filters. The reference system provides independent set-point voltages to the PWM control loops of
each channel, and are programmed via the 4-wire serial port. Output control of the regulators is provided in 15
steps with 400-mV resolution over a range of 7.5 V to 13.1 V. The DACs can also be programmed to force the
PMOSFETs into the fully on pass-through or bypass mode to pass the input voltage to any output.
UVLO circuit and power-up state
The undervoltage lockout (UVLO) circuit controls device operation when the input voltage is below the UVLO
threshold such as during power up or power down. Hysteresis built in to the UVLO detection circuit reduces
sensitivity to noise and ripple on the power supply inputs to the TPS54900. Prior to reaching the UVLO threshold,
the ramp oscillator is disabled so that no switching occurs in the TPS54900, the PMOS transistors are forced
into the off-state, and the registers and DACs are reset. Once the UVLO threshold is reached, the soft-start
sequence begins. If the input voltage falls below the UVLO threshold after the device is programmed and
operating, all four outputs are disabled, the DACs are set to zero volts, and the programming registers are reset.
Subsequently returning VIN above the UVLO threshold requires reinitialization of the phase stagger and
channel voltage programming
soft-start sequence and voltage transitioning
When the supply voltage exceeds the UVLO threshold, the TPS54900 is ready to be programmed via the serial
interface. As each channel is programmed and enabled with a voltage code, the channel DACs begin stepping
the output up from zero volts to the target voltage in 200-mV increments. If the target voltage is 15 V (i.e.,
pass-through mode) the DAC continues to increment in 200-mV steps between 13.1 V and the fully on state.
When a channel is commanded to transition from one voltage level to another, the output steps up (or down)
to the new level in 200-mV increments. The period between each DAC increment is approximately 87 μ s when
the SCLK frequency equals 4.416 MHz. This results in a maximum ramp-up time of 8 ms when stepping from
0 V to 15 V, and a maximum transition time between max and min regulation voltages (7.5 V, 13.1 V) of 4 ms.
The use of small step increments provides a smooth predictable ramp and prevents inadvertent tripping of the
overcurrent limit.
During this transition period, the channel status may be read via the 4-wire serial port using the read protocol.
The data returned is nonzero while channel is transitioning.
oscillator, divider and sync circuit
The TPS54900 has a free-running internal ramp oscillator that operates at a nominal frequency of 450 kHz.
When the 4.416-MHz SCLK signal is present, a synchronous divide-by-eight circuit provides a 552-kHz clock
to synchronize the PWM ramp. The start of the ramp is coincident with every eighth rising edge of SCLK. If the
TPS54900 SCLK pin is driven at a frequency lower than eight times the free-running frequency of the oscillator
(f osc ), it may result in chaotic operation. Care should be taken to ensure that the minimum frequency at the SCLK
input is 4.4 MHz.
phase stagger circuit
When two TPS54900 devices are used as a pair to operate as an 8-channel unit, the PWM ramps in the two
devices can be phase staggered to reduce input ripple and bypass requirements. The initialization command
forces the PWM ramp of the device with its CBS pin tied low to be staggered by four SCLK cycles compared
to the device with its CBS pin forced to a logic high. Note that this command clears the voltage programming
in both devices and disables the outputs. Voltage programming instructions can be issued immediately following
the initialization command.
www.ti.com
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相关代理商/技术参数 |
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| TPS54900PWRG4 | 功能描述:开关变换器、稳压器与控制器 Prog 4-Ch Step Dwn DC/DC Converter RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| TPS54910 | 制造商:TI 制造商全称:Texas Instruments 功能描述:3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) |
| TPS54910EVM-213 | 功能描述:电源管理IC开发工具 9-A 3-4 Vin DC/DC Converter RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| TPS54910PWP | 功能描述:直流/直流开关调节器 3.3V Inp 9A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| TPS54910PWP | 制造商:Texas Instruments 功能描述:IC's |
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