参数资料
型号: TPS57040QDGQRQ1
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10
封装: GREEN, PLASTIC, MSOP-10
文件页数: 20/51页
文件大小: 1871K
代理商: TPS57040QDGQRQ1
VSENSE
COMP
VO
R1
R3
C1
C2
R2
CO
RO
gmea
97 A/V
m
0.8 V
Power Stage
gm
6 A/V
ps
PH
RESR
COUT
RL
b
a
c
VO
RESR
COUT
RL
VC
gmps
fp
fz
Adc
SLVSAP4A
– DECEMBER 2010 – REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
Figure 46. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 47 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS57040-Q1 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage
transconductance. The gmPS for the TPS57040-Q1 is 6A/V. The low-frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
Figure 47. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
Copyright
2010–2011, Texas Instruments Incorporated
27
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