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参数资料
| 型号： | TPS59116RGER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, PQCC24 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, VQFN-24 |
| 文件页数： | 11/36页 |
| 文件大小： | 827K |
| 代理商： | TPS59116RGER |
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TI Information — Selective Disclosure
www.ti.com
SLUSA57 – NOVEMBER 2010
This thermal resistance strongly depends on the board layout. TPS59116 is assembled in a thermally enhanced
PowerPAD package that has exposed die pad underneath the body. For improved thermal performance, this
die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat
sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land
with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.
Further information about PowerPAD and its recommended board layout is described in (SLMA002). This
document is available at http:\\www.ti.com.
Layout Considerations
Certain points must be considered before designing a layout using the TPS59116.
The PCB trace is defined as LL node, which connects to the source of the switching MOSFET, the drain of
the rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
Consider adding a small snubber circuit, consisting of 3
and 1 nF, between LL and PGND in case a
high-frequency ringing is observed on the LL voltage waveform.
All sensitive analog traces such as VDDQSNS, VTTSNS and CS should be placed away from high-voltage
switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.
VLDOIN should be connected to VDDQ output with a short and wide trace. If a different power source is used
for VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with a short and wide
connection.
The output capacitor for VTT should be placed as close as possible to the pin with a short and wide
connection in order to avoid additional ESR and/or ESL of the trace.
VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the
high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitor(s).
Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 m
.
VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding
common impedance to the high current path of the VTT source/sink current.
GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND
to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid
additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.
Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace for
high-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. In case
of using external current sense resistor, apply the same care and connect it to the positive side (ground side)
of the resistor.
PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect to
source of rectifying MOSFET with shortest possible path.
Place a V5FILT filter capacitor (RGE) close to the TPS59116, within 12 mm (0.5 inches) if possible.
The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH,
DRVL or PGOOD.
In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground
plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land pad underneath
the package.
Copyright 2010, Texas Instruments Incorporated
19
Product Folder Link(s): TPS59116
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