参数资料
型号: TPS59116RGER
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, PQCC24
封装: 4 X 4 MM, GREEN, PLASTIC, VQFN-24
文件页数: 36/36页
文件大小: 827K
代理商: TPS59116RGER
TI Information — Selective Disclosure
www.ti.com
SLUSA57 – NOVEMBER 2010
DETAILED DESCRIPTION
The TPS59116 is an integrated power management solution which combines a synchronous buck controller, a
10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin
HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that
required with DDR/DDR2/DDR3 memory systems. The switch mode power supply (SMPS) portion employs
external N-channel MOSFETs to support high current for DDR/DDR2/DDR3 memory’s VDD/VDDQ. The preset
output voltage is selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can be
adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive
on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency
down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a
low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more
accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the
10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink
up to 3-A peak current with only 20-mF (two 10-mF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2
within ±1% of VDDQ. VTT output tracks VTTREF within ±20 mV at no load condition while ±40 mV at full load.
The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin.
This helps reducing power dissipation in sourcing phase. TheTPS59116 is fully compatible to JEDEC DDR/DDR2
specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when
both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the
internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking
discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and
VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the
tracking discharge. These discharge functions can be disabled by selecting non-discharge mode.
VDDQ SMPS, Dual PWM Operation Modes
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.
It supports two control schemes which are a current mode and a proprietary D-CAP mode. D-CAP mode
uses internal compensation circuit and is suitable for low external component count configuration with an
appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external
compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as
ceramic or specialty polymer capacitors.
These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,
TPS59116 works in the D-CAP mode, otherwise it works in the current mode. VDDQ output voltage is
monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the
output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to
VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).
At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET
is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and
VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see
PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback
information indicates insufficient output voltage and inductor current information indicates below the overcurrent
limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or
the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying
MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to
the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load
current.
In the current mode control scheme, the transconductance amplifier generates a target current level
corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During
the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and
when the inductor current signal comes lower than the target current level, the comparator provides SET signal
to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support
various types of output MOSFETs and capacitors. In the D-CAP mode, the transconductance amplifier is
disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference
during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides
SET signal to initiate the next ON state.
Copyright 2010, Texas Instruments Incorporated
9
Product Folder Link(s): TPS59116
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