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| 型号： | TPS61170DRVTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.44 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封装： | 2 X 2 MM, GREEN, PLASTIC, SON-6 |
| 文件页数： | 6/29页 |
| 文件大小： | 689K |
| 代理商： | TPS61170DRVTG4 |
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SLVS789C
– NOVEMBER 2007 – REVISED APRIL 2011
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH. It can be simplified to:
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
Acknowledge is requested by a set RFA bit.
The transmitted device address matches with the device address of the device.
16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512μs
maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal
ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
Note that the acknowledge condition may only be requested if the master device has an open drain output. For
the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500
μA is
recommended for such cases as:
an accidentally requested acknowledge, or
to protect the internal ACKN-MOSFET.
14
Copyright
2007–2011, Texas Instruments Incorporated
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