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| 型号： | TPS62402DRCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 0.6 A DUAL SWITCHING CONTROLLER, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | 3 X 3 MM, GREEN, PLASTIC, SON-10 |
| 文件页数： | 14/43页 |
| 文件大小： | 1155K |
| 代理商： | TPS62402DRCTG4 |
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SLVS681E – JUNE 2006 – REVISED APRIL 2010
Table 1. Addressable Registers for default Fixed Output Voltage Options (PIN DEF_1 = digital input)
DEVICE
REGISTER
DESCRIPTION
DEF_1
A1
A0
D4
D3
D2
D1
D0
PIN
REG_DEF_1_High Converter 1 output voltage setting for
High
0
1
Output voltage setting, see
DEF_1 = High condition. The content of
the register is active with DEF1_ Pin high.
TPS62401,
REG_DEF_1_Low
Converter 1 output voltage setting for
Low
0
Output voltage setting, see
TPS62402,
DEF_1 = Low condition.
TPS62403,
TPS62404
REG_DEF_2
Converter 2 output voltage
Not
1
0
Output voltage setting, see
applicable
Don’t use
1
Table 2. Addressable Registers for Adjustable Output Voltage Options (PIN DEF_1 = analog input)
DEVICE
REGISTER
DESCRIPTION
A1
A0
D4
D3
D2
D1
D0
REG_DEF_1_High
not available
REG_DEF_1_Low
Converter 1 output voltage setting
0
see Table 5
TPS62400
REG_DEF_2
Converter 2 output voltage
1
0
see Table 6
Don’t’ use
1
Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can
be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 34
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 34
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between tLow and tHigh a 0 or 1 is detected.
Acknowledge
The Acknowledge condition is only applied if:
Acknowledge is requested by a set RFA bit
The transmitted device address matches with the device address of the device
16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is 520ms maximum . The Acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was
detected. The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address, or not-correctly-received protocol, no-acknowledge condition is applied;
thus, the internal MOSFET is not turned on and the external pullup resistor pulls MODE/DATA pin high after
tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
NOTE
The acknowledge condition may only be requested in case the master device has an open
drain output.
In case of a push-pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the
current to 500 mA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
MODE Selection
Because the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to
determine when it has to decode the bit stream or to change the operation mode.
Copyright 2006–2010, Texas Instruments Incorporated
21
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