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参数资料
| 型号： | TPS65230A2DCA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO48 |
| 封装： | GREEN, HTSSOP-48 |
| 文件页数： | 29/29页 |
| 文件大小： | 1195K |
| 代理商： | TPS65230A2DCA |
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POWER-UP SEQUENCING
V3p3
(1)
(2)
EN_BCKx
BUCKENABLE
6uA
Enable
Threshold
BUCK A
Enable
BUCKB
Enable
BUCKC
Enable
V
(E
N
p
in
)
Time
Delaytime = 0.2ms/nF
1.2V
(1) Connect EN_BCKx pin to V3P3 to follow the default power-up sequence or
(2) Connect a capacitor from EN_BCKx to GND to generate a custom power-up sequence.
OVER CURRENT PROTECTION
I
=
LIM
R
I
TRIP
10
RDS(ON)
(1)
www.ti.com.................................................................................................................................... SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
ON/OFF control and power sequencing of the three buck regulators is controlled through EN_BCK1, EN_BCK2,
and EN_BCK3 enable pins. Each pin is internally connected to a 6-
A constant-current source and monitored by
a comparator with Schmitt trigger input with defined threshold. Connecting EN_BCKn pin to ground disables
BUCKn and connecting EN_BCKn to V3P3 will enable the respective buck without delay. If more than one buck
enable pin is connected to V3P3 the default startup sequence is BUCK1, BUCK2, BUCK3 and the minimum
startup delay between rails is the soft-start time (typical 1.5 ms) plus 1 ms.
To create a startup-sequence different from the default, capacitors are connected between the EN_BUCKn pins
and ground. At power-up the capacitors are first discharged and then charged to V3P3 level by internal current
sources (6
A typical) creating a constant-slope voltage ramp. A regulator is enabled when its EN pin voltage
crosses the enable threshold (typical 1.2 V). A delay of 0.2 ms is generated for each 1-nF of capacitance
connected to the enable pin. If two enable pins are pulled high while the third regulator is starting up, the default
sequence will be applied to enable the remaining two regulators. To override default power-up sequence it is
recommended that delay times differ by more than the soft-start time (typical 1.3 ms) plus 1 ms.
In I2C mode regulators can also be enabled by setting their respective EN bits in the ENABLE register. The same
startup-time limitations and arbitration rules apply in I2C mode as described above.
Figure 2. Customizing the Power-Up Sequence
Over current protection (OCP) for BUCK1 is achieved by comparing the drain-to-source voltage of the low-side
MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the external
resistor connected between the TRIP pin and ground. Over current threshold is calculated as Equation 1.
ITRIP has a typical value of 10
A at 25°C and a temperature coefficient of 3700 ppm/°C to compensate the
temperature dependency of the MOS RDS(ON). The TPS65230 and TPS65231 support cycle-by-cycle over current
limiting control which means that the controller compares the drain-to-source voltage of the low-side FET to the
set-point voltage once per switching cycle and blanks out the next switching cycle if an over-current condition is
detected. If in the following cycle over current condition is detected again, the controller blanks out 2, then 4, 8,
and up to 16 cycles before turning on the high-side driver again. In an over current condition the current to the
load exceeds the current to the output capacitor thus the output voltage will drop, and eventually cross the under
Copyright 2009, Texas Instruments Incorporated
9
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