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参数资料
| 型号： | TPS65230A2DCA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO48 |
| 封装： | GREEN, HTSSOP-48 |
| 文件页数： | 5/29页 |
| 文件大小： | 1195K |
| 代理商： | TPS65230A2DCA |
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VBCK3[1:0 ]
00 – 0%
01 – 5%
10 – 10%
11 – 15%
VBCK2[1:0 ]
00 – 0%
01 – 5%
10 – 10%
11 – 15%
VBUCK3
VBUCK2
VBUCK1
VCTRL pin
orVCTRL bit
Time
2222A
10K
47.5K
4.7K
TouC
USBFLG2/nINT
V6 V
3 .3V
I
2C BUS OPERATION
G3
G2
A1
A0
R/nW
ACK
Start
G1
G0
A2
S7
S6
S2
S1
S5
S4
S3
S0
ACK
D7
D6
D2
D1
D5
D4
D3
D0
ACK
Stop
Slave Address + R/nW
Sub Address
Data
www.ti.com.................................................................................................................................... SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
I2C operation also offers output voltage adjustment options for BUCK2 and BUCK3. This is feature is useful to
reduce power dissipation in the system by lowering the supply voltages when the system is in idle state. Output
voltage can be scaled down by 5, 10 and 15% depending on the VBCKn[1:0] bit settings in the VADJUST
register. Settings are activated when the USBFLG1/VCTRL pin is pulled high and are deactivated when the pin is
pulled low. This allows for fast output voltage transition without involvement of the I2C interface. Alternatively the
settings can be activated by setting the the VCTRLx bits of the ENABLE register.
Figure 4. BUCK2 and BUCK3 Output Voltages
Figure 5. Circuit for Level-Shifting and Inverting nINT Signal
The TPS65230 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Figure 6. Subaddress in I2C Transmission
Start —
Start condition
G(3:0) —
Group ID: 1001
A(2:0) —
Device address: 000
R/nW —
Read/not write select bit
Copyright 2009, Texas Instruments Incorporated
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