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| 型号： | TPS659102A1RSLR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 75/93页 |
| 文件大小： | 1014K |
| 代理商： | TPS659102A1RSLR |
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SWCS046I
– MARCH 2010 – REVISED JULY 2011
7
6
5
4
3
2
1
0
RSVD
VIO_SETOFF
VDD3_SETOFF
VDD2_SETOFF
VDD1_SETOFF
SPARE_SETOFF
DEFAULT_VOLT
Bits
Field Name
Description
Type
Reset
7
DEFAULT_VOLT
When 1, default voltages (registers value after switch-on) will be used to
RW
0
turned-on supplies during SLEEP to ACTIVE state transition.
When 0, voltages programmed before the ACTIVE to SLEEP state
transition will be used to turned-on supplies during SLEEP to ACTIVE
state transition.
6:5
RSVD
Reserved bit
RO
0x0
R returns
0s
4
SPARE_SETOFF
Spare bit
RW
0
3
VDD3_SETOFF
When 1, SMPS is turned off during device SLEEP state.
RW
0
When 0, No effect.
2
VDD2_SETOFF
When 1, SMPS is turned off during device SLEEP state.
RW
0
When 0, No effect.
1
VDD1_SETOFF
When 1, SMPS is turned off during device SLEEP state.
RW
0
When 0, No effect.
0
VIO_SETOFF
When 1, SMPS is turned off during device SLEEP state.
RW
0
When 0, No effect.
Table 68. EN1_LDO_ASS_REG
Address Offset
0x45
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined
though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect : LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN1
VPLL_EN1
VAUX33_EN1
VAUX2_EN1
VAUX1_EN1
VDIG2_EN1
VDIG1_EN1
VMMC_EN1
Bits
Field Name
Description
Type
Reset
7
VDAC_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
6
VPLL_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
5
VAUX33_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
4
VAUX2_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
3
VAUX1_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
2
VDIG2_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
1
VDIG1_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
VMMC_EN1
Setting supply state control though SCLSR_EN1 signal
RW
0
Copyright
2010–2011, Texas Instruments Incorporated
77
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