参数资料
型号: TPS70702PWP
厂商: Texas Instruments, Inc.
元件分类: 线性稳压
英文描述: DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
中文描述: 两用低压差最多可劈开电压DSP系统序列电源电压稳压器的输出
文件页数: 18/34页
文件大小: 505K
代理商: TPS70702PWP
RESET
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VI
VOUT1
MR1
0.1
F
10
F
10
F
0.1
F
MR2
EN
TPS707xxPWP
(Fixed Output Option)
>2 V
<0.7 V
250 k
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
sequencing timing diagrams (continued)
application conditions not shown in block diagram:
VIN1 and VIN2 are tied to the same fixed input
voltage greater than the VUVLO; SEQ is tied to
logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
explanation of timing diagrams:
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken low, VOUT2
turns on. VOUT1turnsonafterVOUT2reaches83%
of its regulated output voltage. When VOUT1
reaches 95% of its regulated output voltage, PG1
(tied to MR2) goes to logic high. When both VOUT1
and VOUT2 reach 95% of their respective
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When a fault on
VOUT2 causes it to fall below 95% of its regulated
output voltage, RESET returns to logic low and VOUT1 begins to power down because SEQ is high. When VOUT1
falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low.
83%
95%
83%
95%
120 ms
ENABLE
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
NOTE A: t1 – Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
t1
(see Note A)
Fault on VOUT2
Figure 40. Timing When VOUT2 Faults Out
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