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| 型号： | TPS70758PWPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封装： | GREEN, PLASTIC, HTSSOP-20 |
| 文件页数： | 15/38页 |
| 文件大小： | 626K |
| 代理商： | TPS70758PWPR |
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APPLICATION INFORMATION
Sequencing Timing Diagrams
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
TPS707xxPWP
(FixedOutputOption)
VI
VOUT1
MR1
0.1 mF
RESET
10 mF
0.1 mF
MR2
EN
>2 V
<0.7 V
250 kW
83%
95%
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQ
95%
83%
NOTE A: t1 Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70745, TPS70748
TPS70751, TPS70758
TPS70702
SLVS291D – MAY 2000 – REVISED DECEMBER 2007
This section provides a number of timing diagrams
showing
how
this
device
functions
in
different
configurations.
Application condition: VIN1 and VIN2 are tied to the
same fixed input voltage greater than the VUVLO; SEQ
is tied to logic low; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
EN is initially high; therefore, both regulators are off
and PG1 and RESET are at logic low. With SEQ at
logic low, when EN is taken to logic low, VOUT1 turns
on. VOUT2 turns on after VOUT1 reaches 83% of its
regulated output voltage. When VOUT1 reaches 95%
of its regulated output voltage, PG1 (tied to MR2)
goes to logic high. When both VOUT1 and VOUT2 reach
95% of their respective regulated output voltages and
both MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120ms delay.
When EN is returned to logic high, both devices
power down and both PG1 (tied to MR2) and RESET
return to logic low.
Figure 36. Timing when SEQ = Low
22
Copyright 2000–2007, Texas Instruments Incorporated
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