参数资料
型号: TPS73533DRVT
厂商: Texas Instruments
文件页数: 3/27页
文件大小: 0K
描述: IC REG LDO 3.3V .5A 6-SON
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 3.3V
输入电压: 最高 6.5V
电压 - 压降(标准): 0.28V @ 500mA
稳压器数量: 1
电流 - 输出: 500mA(最小值)
电流 - 限制(最小): 800mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 6-WDFN 裸露焊盘
供应商设备封装: 6-SON 裸露焊盘(2x2)
包装: 标准包装
产品目录页面: 1065 (CN2011-ZH PDF)
其它名称: 296-24289-6

TPS735xx
SBVS087K – JUNE 2008 – REVISED AUGUST 2013
THERMA L INFORMATION
TPS735xx (2)
THERMAL METRIC (1)
DRB
8 PINS
DRV (3)
6 PINS
UNITS
θ JA
θ JCtop
Junction-to-ambient thermal resistance (4)
Junction-to-case (top) thermal resistance (5)
47.8
83
50.2
59
Junction-to-board thermal resistance
θ JB
ψ JT
ψ JB
θ JCbot
(6)
Junction-to-top characterization parameter (7)
Junction-to-board characterization parameter (8)
Junction-to-case (bottom) thermal resistance (9)
N/A
2.1
17.8
12.1
N/A
0.1
30.1
8.3
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A .
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a)
i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
. ii. DRV: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. Due to size limitation of thermal
pad, 0.8-mm pitch array is used which is off the JEDEC standard.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii DRV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Power dissipation may limit operating range.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψ JT , estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θ JA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψ JB , estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θ JA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright ? 2008–2013, Texas Instruments Incorporated
3
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