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参数资料
| 型号： | TRF2056PWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20 |
| 封装： | PLASTIC, SOP-20 |
| 文件页数： | 6/24页 |
| 文件大小： | 327K |
| 代理商： | TRF2056PWR |
TRF2056
LOW VOLTAGE 1.2GHz FRACTIONALN/INTEGERN SYNTHESIZER
SLWS111– NOVEMBER 2000
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
For contiguous channels, the following rules must be observed:
For PR = 01: 61
≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 63, which yields minimum and maximum divide ratios of 4032
and 266303, respectively.
For PR = 10: 14
≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 15, and 0 ≤ NM3 ≤ 15, which yields minimum and maximum divide
ratios of 1096 and 264335, respectively.
main divider – synchronization
The A-Word is loaded only when a main divider synchronization signal is active. This prevents phase jumps
when reprogramming the main divider. The synchronization signal is generated by the main divider, and it is
active while the main divider is counting down from the programmed value. When the main divider reaches its
terminal count, a main divider output pulse is sent to the main phase detector. Also at this time, the loading of
the A-Word is disabled. Therefore, to correctly load the new A-Word, STROBE must be active high for at least
a minimum number of VCO input cycles at RFIN.
main divider – fractional accumulator
The TRF2056 main synthesizer loop can operate as a traditional integer-N feedback PLL or as a fractional-N
feedback PLL. The integer-N feedback loop divides the VCO frequency by integer values of N, which results
in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides
the VCO frequency by an integer term plus a fractional term, which results in phase detector reference
comparisons at integer multiples of the desired system channel spacing.
Integer-N division: VCO frequency
N = phase detector reference frequency
= channel spacing
Fractional-N division: VCO frequency
(N + NF/FMOD) = phase detector reference frequency
= FMOD
× channel spacing
where 0
≤ NF < FMOD and 1 ≤ FMOD ≤ 16.
Because the main counter and prescaler sections cannot divide by a fraction of an integer, the fractional-N
division is accomplished by averaging main divider cycles by N and N+1. A fractional accumulator is
programmed with values of NF and FMOD to control the main counter and prescaler sections to divide by N
or N+1.
The fractional accumulator operates modulo FMOD and is incremented by NF at the completion of each main
divider cycle. When the fractional accumulator overflows, division by N+1 occurs. Otherwise, the main counters
and prescaler divide by N; division by N+1 is transparent to the user. Table 3 shows the contents of the fractional
accumulator and the resulting N or N+1 division for two fractional division ratios.
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