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| 型号： | TRK-MPC5604P |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 68/104页 |
| 文件大小： | 0K |
| 描述： | 5604P TTK BD |
| 设计资源： | TRK-MPC5604P Component List TRK-MPC5604P Schematic |
| 标准包装： | 1 |
| 系列： | MPC56xx |
| 类型： | MCU |
| 适用于相关产品： | MPC5604P |
| 所含物品： | 板，线缆，CD，DVD |
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MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale
66
CJITTER T CLKOUT period
jitter6,7,8,9
Short-term jitter10
fSYS maximum
44
% fCLKOUT
Long-term jitter (avg.
over 2 ms interval)
fPLLIN = 16 MHz
(resonator)
, fPLLCLK at
64 MHz, 4,000 cycles
—10
ns
tlpll
D PLL lock time 11, 12
—
200
s
tdc
D Duty cycle of reference
—40
60
%
fLCK
D Frequency LOCK range
—
66
% fSYS
fUL
D Frequency un-LOCK range
—
-18
18
% fSYS
fCS
fDS
D Modulation depth
Center spread
±0.25
±4.013
% fSYS
Down spread
0.5
8.0
fMOD
D Modulation frequency14
—
70
kHz
1 VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2 Considering operation with PLL not bypassed
3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked
mode.
4 Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
5 fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6 This value is determined by the crystal manufacturer and board design.
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
8 Proper PC board layout procedures must be followed to achieve specifications.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 29. FMPLL electrical characteristics (continued)
Symbol C
Parameter
Conditions1
Value
Unit
Min
Max
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TRK-MPC5606B | 制造商:Freescale Semiconductor 功能描述:MPC5606B 144PIN REV 2.1 - Boxed Product (Development Kits) 制造商:Freescale Semiconductor 功能描述:STARTERTRAK DEV BOARD MPC5606B 制造商:Freescale Semiconductor 功能描述:MPC560 QORIVVA STARTER TRAK 制造商:Freescale Semiconductor 功能描述:PRIMARY PLATFORM ((NW)) 制造商:Freescale Semiconductor 功能描述:MPC560, QORIVVA, STARTER TRAK, DEV KIT 制造商:Freescale Semiconductor 功能描述:MPC5606B 144pin 制造商:Freescale Semiconductor 功能描述:EVAL KIT, MPC560B STARTERTRAK AUTO BODY ELECT; Silicon Manufacturer:Freescale; Core Architecture:Power Architecture; Core Sub-Architecture:Power Architecture; Silicon Core Number:MPC5xxx; Silicon Family Name:Qorivva |
| TRK-MPC5606B | 制造商:Freescale Semiconductor 功能描述:PRIMARY PLATFORM ((NW)) |
| TRK-MPC5634M | 功能描述:开发板和工具包 - 其他处理器 TRAK 5634M 144pn R2.1 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| TRK-USB-MPC5602P | 功能描述:开发板和工具包 - 其他处理器 STRAKMiniUSB RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| TRK-USB-MPC5604B | 功能描述:开发板和工具包 - 其他处理器 MiniUSB MPC5604B RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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