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| 型号： | TS-MAC-P2-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 32/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI ECP2 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACP2UT4 |
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Lattice Semiconductor
Functional Description
Successful Transmission of a 64-Byte Frame -Tx MAC Application Interface
The assertion of tx_fifoavail indicates a frame is ready to be transmitted. It does not trigger the MAC transmit pro-
cess. The MAC actually pre-reads the FIFO as soon as tx_fifoempty goes low (indicating data is present in the Tx
FIFO). The tx_fifoempty signal, the tx_fifoavail signal and the MAC Tx state machine all determine when to read the
Tx FIFO. The TSMAC IP core reads the FIFO and the data is transmitted until tx_fifoeof is asserted. Once the
frame is transmitted, tx_staten is asserted to qualify the statistic vector, tx_statvec. The signal tx_done is asserted
to indicate a successful transmission. This is shown in Figure 2-12 , and described as follows in detail.
Figure 2-12. Transmission of a 64-Byte Frame without Error
txmac_clk
tx_fifoavail
4
tx_fifodata[7:0]
1
2
62
63
64
tx_macread
tx_staten
tx_staten[31:0]
tx_fifoeof
tx_fifoempty
1
2
3
5
6
Valid
tx_discfrm
tx_done
1.The Tx FIFO is initially empty (tx_fifoempty is asserted) and the MAC Tx state machine is in an idle state.
2.The client interface begins loading the Tx FIFO. Once the tx_fifoempty signal is de-asserted the tx_macread is
asserted and the MAC Tx state machine goes into a transmit state. The MAC performs a “pre-read” and continues
to assert the tx_macread as long as the Tx FIFO is not empty (tx_fifoempty stays low). The pre-read typically is 7 to
8 bytes.
3.If tx_fifoavail is low after the pre-read, the Tx MAC will de-assert the tx_macread until the tx_fifoavail is asserted.
4.tx_fifoavail is set high by the client interface indicating all bytes of the packet are now available for transmission.
The Tx MAC re-asserts tx_macread and reads all bytes until tx_fifoeof indicates the last byte.
5.Once the complete packet is read out by the Tx MAC, it checks the status of tx_fifoempty and tx_fifoavail again. If
either tx_fifoavail is low or tx_fifoempty is high at the end of the packet, the MAC de-asserts tx_macread. If
tx_fifoavail is high and tx_fifoempty is low, (FIFO is not empty) the Tx MAC will do another pre-read (not shown in
this figure) and start the transmit process over.
6.Once the frame is transmitted, tx_staten is asserted to qualify the statistic vector, tx_statvec. The signal tx_done
is asserted to indicate a successful transmission.
IPUG51_03.0, December 2010
32
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| TS-MAC-E3-UT4 | SITE LICENSE ETH MAC TRI ECP3 |
| TS-MAC-E2-UT4 | SITE LICENSE ETH MAC TRI EC/ECP |
| VI-J0T-EZ-F1 | CONVERTER MOD DC/DC 6.5V 25W |
| VI-J0T-EY-S | CONVERTER MOD DC/DC 6.5V 50W |
| VI-J0R-EZ-F4 | CONVERTER MOD DC/DC 7.5V 25W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACPMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-PM-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-PM-U4 | 功能描述:开发软件 Ethernet MAC Tri-Speed RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-PM-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACSCU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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