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| 型号： | TS(X)PC603PVAU/T6ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 18/38页 |
| 文件大小： | 704K |
| 代理商： | TS(X)PC603PVAU/T6ME |
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TSPC603p
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5.1.7.2. Supervisor-Level SPRs
The 603p also contains SPRs that can be accessed only by supervisor-level software. These registers consist of the following :
D The 32-bit DSISR defines the cause of data access and alignment exceptions.
D The data address register (DAR) is a 32-bit register that holds the address of an access after an alignment or DSI exception.
D Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception
after a programmable delay.
D The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for pages. (Note that physical
address is referred to as real address in the architecture specification).
D The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 603p for saving the address of the instruc-
tion that caused the exception, and the address to return to when a Return from Interrupt (rfi) instruction is executed.
D The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status on exceptions and to restore
machine status when an rfi instruction is executed.
D The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
D The external access register (EAR) is a 32-bit register that controls access to the external control facility through the External
Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions.
D The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. The TB consists of two
32-bit fields - time base upper (TBU) and time base lower (TBL).
D The processor version register (PVR) is a 32-bit, read-only register that identifies the version (model) and revision level of the
PowerPC processor.
D Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT registers, divided into four pairs of data BATs
(DBATs) and four pairs of instruction BATs (IBATs). See Figure 15 for a list of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific to the 603p :
D The DMISS and IMISS registers are read-only registers that are loaded automatically upon an instruction or data TLB miss.
D The HASH1 and HASH2 registers contain the physical addresses of the primary and secondary page table entry groups (PTEGs).
D The ICMP and DCMP registers contain a duplicate of the first word in the page table entry (PTE) for which the table search is
looking.
D The required physical address (RPA) register is loaded by the processor with the second word of the correct PTE during a page
table search.
D The hardware implementation (HID0 and HID1) registers provide the means for enabling the 603p”s checkstops and features,
and allows software to read the configuration of the PLL configuration signals.
D The instruction address breakpoint register (IABR) is loaded with an instruction address that is compared to instruction addresses
in the dispatch queue. When an address match occurs, an instruction address breakpoint exception is generated.
Figure 15 shows all the 603p registers available at the user and supervisor level. The number to the right of the SPRs indicate the
number that is used in the syntax of the instruction operands to access the register.
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