- 您现在的位置：买卖IC网 > PDF目录297617 > TS(X)PC603PVGU/T8ME 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 PDF资料下载
参数资料
| 型号： | TS(X)PC603PVGU/T8ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | CBGA-255 |
| 文件页数： | 28/38页 |
| 文件大小： | 704K |
| 代理商： | TS(X)PC603PVGU/T8ME |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
TSPC603p
34/38
The instruction pipeline in the 603p has four major pipeline stages, described a follows :
D The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next
instruction fetch. Additionally, the BPU decodes branches during the fetch stage and folds out branch instructions before the dis-
patch stage if possible.
D The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage, and determining
which of the instructions are eligible to be dispatched in the current cycle. in addition, the source operands of the instructions are
read from the appropriate register file and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch
pipeline stage, the dispatched instructions and their operands are latched by the appropriate execution unit.
D During the execute pipeline stage each execution unit that has an executable instruction executes the selected instruction (per-
haps over multiple cycles), writes the instruction’s result into the appropriate rename register, and notifies the completion stage
that the instruction has finished execution. In the case of an internal exception, the execution unit reports the exception to the
completion/writeback pipeline stage and discontinues instruction execution until the exception is handled. The exception is not
signaled until that instruction is the next to be completed. Execution of most floating-point instructions is pipelined within the FPU
allowing up to three instructions to be executing in the FPU concurrently. The pipeline stages for the floating-point unit are multiply,
add, and round-convert. Execution of most load/store instructions is also pipelined. The load/store units has two pipeline stages.
The first stage is for effective address calculation and MMU translation and the second stage is for accessing the data in the cache.
D The complete/writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the rename
registers to the GPRs and FPRs as instructions are retired. If the completion logic detects an instruction causing an exception,
all following instructions are cancelled, their execution results in rename registers are discarded, and instructions are fetched from
the correct instruction stream.
A superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in
parallel. The 603p has five independent execution units, one each for integer instructions, floating-point instructions, branch instruc-
tions, load/store instructions, and system register instructions. The IU and the FPU each have dedicated register files for maintaining
operands (GPRs and FPRs, respectively), allowing integer calculations and floating-point calculations to occur simultaneously with-
out interference.
Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction timing among various Pow-
erPC processors varies accordingly.
6. PREPARATION FOR DELIVERY
6.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
6.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883
and guarantying the parameters not tested at temperature extremes for the entire temperature range.
7. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devi-
ces have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recom-
mended :
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
相关PDF资料 |
PDF描述 |
|---|---|
| TS(X)PC603PMGB/C6LE | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| TSSH-119-01-TM-DH | 38 CONTACT(S), MALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER |
| TSSH-121-01-F-DH | 42 CONTACT(S), MALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER |
| TSSH-121-01-FM-DH | 42 CONTACT(S), MALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER |
| TSSH-123-01-STL-DH | 46 CONTACT(S), MALE, RIGHT ANGLE TWO PART BOARD CONNECTOR, SOLDER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSXPC860SRVZQU66D | 功能描述:IC MPU POWERQUICC 66MHZ 357PBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:60 系列:SCC 处理器类型:Z380 特点:全静电 Z380 CPU 速度:20MHz 电压:5V 安装类型:表面贴装 封装/外壳:144-LQFP 供应商设备封装:144-LQFP 包装:托盘 |
| TSXPCX1031 | 制造商:Schneider Electric 功能描述:CABLE TO PC SERIAL PORT (SUB-D9) 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE 制造商:Schneider Electric 功能描述:MULTI-FUNCTION COMMUNICATION CABLE 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE; Accessory Type:Programmable Cable; For Use With:Schneider Non-Ethernet Based Twido PLCs ;RoHS Compliant: Yes 制造商:Schneider Electric 功能描述:Programme cable for twido-nano-micro PLC |
| TSXPLP01 | 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 ;ROHS COMPLIANT: YES 制造商:Schneider Electric 功能描述:TSXPLP01 PLC replacement battery |
| TSXPLP101 | 制造商:Schneider Electric 功能描述:BATTERY TSX 37 QTY.10, TSXPLP101 |
| TSXPRGLDR | 制造商:Schneider Electric 功能描述:PROGRAM LOADER FOR 07/37 |
发布紧急采购，3分钟左右您将得到回复。