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| 型号： | TS(X)PC603PVGU/T8ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | CBGA-255 |
| 文件页数： | 31/38页 |
| 文件大小： | 704K |
| 代理商： | TS(X)PC603PVGU/T8ME |
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TSPC603p
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9. CLOCK RELATIONSHIPS CHOICE
The 603p microprocessors offer customers numerous clocking options. An internal phase-lock loop synchronizes the processor
(CPU) clock to the bus or system clock (SYSCLK) at various ratios. These ratios allow the designer to utilize the following options :
D Low-speed, low-cost memory systems with economical, low-cost processors.
D Low-speed, economical memory systems isolated from very high-speed processor cores and internal cache.
D High-speed, performance oriented memory systems with maximum achievable processor core and internal cache frequencies.
D Embedded systems with unusual bus speeds dictated by system equirements other than the processor.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in
frequency and phase by a frequency/phase detector which compares the input bus frequency (SYSCLK frequency) to a submultiple
of the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode).
In the Table 17, the vertical scale represents the bus frequency (SYSCLK) and the horizontal scale represents the bus mode.
Table 17 : CPU frequencies for common bus frequencies and multipliers
Bus to CPU Multiplier
2:1
5:2
3:1
7:2
4:1
9:2
5:1
11:2
6:1
Bus frequency (MHz)
CPU frequency (MHz)
66.67
133
167
200
233
267
300
333
367
400
60
120
150
180
210
240
270
300
330
360
50
100
125
150
175
200
225
250
275
300
40
80
100
120
140
160
180
200
220
240
37.6
75
94
113
131
150
169
188
206
225
33.33
67
83
100
117
133
150
167
183
200
25
50
63
75
88
100
113
125
138
150
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